Senior Digital Design Engineer - SoC IPs & Automation

Cadence Design Systems; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence Design Systems seeks a digital design engineer to design and integrate IPs in SoCs based on customer specifications. You will perform Lint/CDC checks, create synthesis constraints, and support verification and physical design teams. The role emphasizes automation, cross‑functional collaboration, and adherence to PPA goals.

Requires 5–8 years in digital design with Verilog/SystemVerilog, AMBA protocols, and scripting skills. A strong team fit with excellent communication is essential.

Qualifications

• B.E./B.Tech/M.Tech with 5–8 years of digital design experience.
• Strong knowledge of digital design fundamentals and Verilog/SystemVerilog.
• Experience with Lint/CDC tools and setting up flows from scratch.
• Familiar with synthesis constraints and STA; synthesis tools a plus.
• Familiarity with simulation tools (Xcelium/Verisium) for verification.
• AMBA protocols and other ARM IPs a plus; high‑speed IPs (PCIe/Ethernet/DDR) a plus.
• Proficient in Python/Perl/Tcl scripting for automation.
• Good communication for cross‑functional collaboration.

Responsibilities

• Design and integration of IPs in SoC per customer specs.
• Perform Lint/CDC checks and resolve related issues.
• Create synthesis constraints and perform basic synthesis for PPA.
• Create detailed Microarchitectural Specification documents.
• Support verification with test plans, coverage analysis, and debugging.
• Assist physical design teams for implementation needs.
• Automate repetitive tasks with innovative solutions.
• Collaborate across teams for effective project execution.

Skills

Digital design fundamentals

Verilog/SystemVerilog

Python scripting

Cross-functional collaboration

Education

B.E./B.Tech/M.Tech

Tools

Lint/CDC tools

Synthesis tools

STA tooling

Xcelium/Verisium

AMBA protocols

PCIe IPs

Ethernet IPs

DDR IPs

Job description

Cadence Design Systems seeks a digital design engineer to design and integrate IPs in SoCs based on customer specifications. You will perform Lint/CDC checks, create synthesis constraints, and support verification and physical design teams. The role emphasizes automation, cross‑functional collaboration, and adherence to PPA goals.

Requires 5–8 years in digital design with Verilog/SystemVerilog, AMBA protocols, and scripting skills. A strong team fit with excellent communication is essential.