Senior CPU RTL Engineer, Silicon

Google; Portland (OR); Vor Ort; USD 163.000 - 236.000; Vollzeit

Benefits dieser Stelle

Equity

Bonus target

Zusammenfassung

Google is seeking a senior CPU RTL design engineer to contribute to frontend designs and the next generation of microarchitecture for its custom silicon. You will collaborate with architects to evaluate performance and power trade-offs, delivering production-quality designs that meet PPA goals.

The role emphasizes experience with RTL, digital logic, and Verilog/SystemVerilog in a fast-paced, hardware-centric environment.

Qualifikationen

• Bachelor's degree required in Electrical/Computer Engineering, CS, or related field.
• 8+ years of experience with digital logic design, RTL design concepts, and Verilog/SystemVerilog.
• Experience with logic synthesis to optimize RTL, performance and power, including low-power techniques.

Aufgaben

• Contribute to CPU frontend designs, emphasizing microarchitecture and RTL design for the next generation CPU.
• Propose performance-enhancing microarchitecture features with efficiency in mind and study trade-offs with architects/performance teams.
• Communicate pros/cons of microarchitecture changes and assist in final decisions.
• Deliver designs meeting Power, Performance and Area goals with production quality.
• Familiarize with techniques for at least one processor functional block and translate into design constructs for performance modeling.

Kenntnisse

RTL design

Digital logic

Verilog/SystemVerilog

Ausbildung

Bachelor's degree in EE/CE/CS or equivalent

Master's or PhD preferred (computer architecture focus)

Jobbeschreibung

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; Portland, OR, USA; Austin, TX, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a different team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies.
• Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
• Deliver designs meeting Power, Performance and Area (PPA) goals with production quality.
• Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .