Lead Circuit Design Engineer for ASICs & Low-Power

Apple Inc.; Beaverton (OR); On-site; USD 142,000 - 263,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon, seeks a Circuit Design Engineering Lead within the Digital Design Engineering group to guide a small team and advance high‑performance, low‑power standard‑cell design. You’ll own critical circuit blocks and drive PPA improvements for cutting‑edge ASICs.

You'll collaborate across CPU/SOC/GPU teams, manage QA and PDV workflows, and coordinate with foundries on iPDK and DRM requirements while migrating to new PDKs. Relocation support may be available.

Qualifications

• Bachelor's Degree plus minimum 3 years of experience.
• 3+ years of experience in Standard cells circuit development.
• Experience leading and mentoring a small team.
• Experience in designing standard cells, Power Management Cells and flop designs.
• Knowledge of DRM, DRC/LVS decks and iPDK requirements.

Responsibilities

• Drive development of high performance, low power standard cells to improve PPA.
• Develop level shifters and retention designs for low power.
• Collaborate with CPU/SOC/GPU teams for chip-level integration.
• Oversee QA checks and develop new methodologies.
• Coordinate with foundries on layout checkers and iPDK requirements.
• Plan and drive development of designs and tech node enablement.
• Manage migration to new PDK and PDV of standard cells and releases.

Skills

Standard cells circuit development

Team leadership

Interpersonal skills

Cross-functional collaboration

Perl or TCL scripting

Education

Bachelor's Degree

Tools

Virtuoso

DRM

DRC/LVS decks

PDV flows

Job description

Apple Inc. in Beaverton, Oregon, seeks a Circuit Design Engineering Lead within the Digital Design Engineering group to guide a small team and advance high‑performance, low‑power standard‑cell design. You’ll own critical circuit blocks and drive PPA improvements for cutting‑edge ASICs.

You'll collaborate across CPU/SOC/GPU teams, manage QA and PDV workflows, and coordinate with foundries on iPDK and DRM requirements while migrating to new PDKs. Relocation support may be available.