Low-Power Physical Design Engineer (7nm+)

Apple Inc.; Cupertino (CA); Hybrid; USD 174.000 - 225.000; Vollzeit

Zusammenfassung

Apple Inc. in Cupertino, California, is seeking a Senior IC Design Engineer to lead power reduction and physical design for advanced node SoCs.

You will perform static and dynamic power analysis, implement low power techniques, fix violations, and drive tape-out readiness with partitioning, floorplanning, and ECOs. You will develop CAD tool flows, script in TCL/Perl/Python, collaborate with logic design, and push design closure through sign-off for timing, PDV, and reliability.

Qualifikationen

• Master's degree or foreign equivalent in Computer Engineering or related field.
• 3 years of experience in the job offered or related occupation.
• Utilize Innovus or Fusion Compiler APR tools to perform implementation design and support execution of tasks.
• Tune implementation design flows and methodologies to improve power, performance, and area.
• Perform static timing analysis and apply timing convergence techniques; debug LVC/DRC violations.
• Perform physical design on advanced technology nodes (7nm and below) with CMOS fabrication knowledge.
• Perform block level physical design, including floor planning, placement, clock tree synthesis, routing, and ECO steps.
• Utilize lower power design techniques including clock gating, power gating, and multi-voltage domains.

Aufgaben

• Analyze and perform static and dynamic power reduction of advanced SoC designs; meet power target goals.
• Implement low power techniques and complete ECOs to fix identified design violations.
• Develop CAD tool flows and automation for design efficiency.
• Execute chip/partition floor planning, pin assignment, macro placement, and evaluate logic placement to improve power, performance, and area.
• Work with the logic design team to align partition architecture with early physical design considerations; drive signoff closure for partitions.

Jobbeschreibung

Apple Inc. in Cupertino, California, is seeking a Senior IC Design Engineer to lead power reduction and physical design for advanced node SoCs.

You will perform static and dynamic power analysis, implement low power techniques, fix violations, and drive tape-out readiness with partitioning, floorplanning, and ECOs. You will develop CAD tool flows, script in TCL/Perl/Python, collaborate with logic design, and push design closure through sign-off for timing, PDV, and reliability.