Ultra-Low Power Digital Circuit Engineer

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 149,000 - 218,000; Full time

Benefits offered by this job

Employee stock purchase plan

Discretionary RSUs

Medical and dental coverage

Relocation assistance

Job summary

Apple Inc. in Cupertino, CA is seeking engineers to design high-performance, ultra-low power circuits and SRAM macros. You will perform transistor-level design, Verilog coding, SPICE simulations, and margin verification across process, voltage, and temperature. Collaboration with layout and power teams is essential.

Role emphasizes circuit methodology, PPA targets, and close integration with physical design to achieve top-tier design quality. Relocation may be provided where applicable.

Qualifications

• Master's degree in Electrical Engineering or related field with 2+ years of experience.
• Experience in high-performance and ultra-low power circuit design.
• Transistor-level circuit design and VLSI design experience.
• Experience with SRAM macro design and aggressive PPA targets.
• Experience using HSPICE for margin analysis across voltages and temperatures.
• Verilog coding and behavioral model verification.
• Collaborating with physical design teams for circuit integration.

Responsibilities

• Collaborate with multiple engineering fields to bring products to market.
• Develop custom circuits to improve power efficiency.
• Define specifications and perform design, simulation, and margin verification across PVT.
• Work with layout team to ensure layout quality and timing closure.

Skills

High performance circuits

Ultra-low power design

Transistor level design

Verilog

Static timing analysis

Place & Route (PnR)

SPICE/HSPICE simulation

VLSI design

Education

Master's degree in Electrical Engineering or related field

Tools

HSPICE

PNR tools

SPICE simulators

Job description

Apple Inc. in Cupertino, CA is seeking engineers to design high-performance, ultra-low power circuits and SRAM macros. You will perform transistor-level design, Verilog coding, SPICE simulations, and margin verification across process, voltage, and temperature. Collaboration with layout and power teams is essential.

Role emphasizes circuit methodology, PPA targets, and close integration with physical design to achieve top-tier design quality. Relocation may be provided where applicable.