Advanced Custom Circuits Engineer for ASICs & ML Accelerators

Apple Inc.; Beaverton (OR); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. is seeking Circuits Engineers to design advanced custom digital megacells for high-performance SOCs. You will develop circuits to improve power efficiency and work with power teams to set specifications.

The role involves SPICE verification, mixed-signal considerations, and silicon bring up, with close collaboration to layout and design teams. A BS and 3+ years in the field are required, with experience in advanced technology nodes and low-power design.

Qualifications

• BS and a minimum of 3 years of relevant industry experience.
• Experience in design of advanced technology nodes.
• Experience in design of low voltages / low power custom circuits.
• Knowledge in ML accelerators, SRAMs, non-volatile memories, weak/moderate inversion circuits, ultra-low power amplifiers, DC/DC converters, high-speed clocking, and TDCs.

Responsibilities

• Develop custom circuits to improve chip power efficiency.
• Work with power team, PD and architects to define specifications and requirements.
• Perform design, analysis, modeling/simulation, circuit level specifications, schematic capture, spice simulation / margin verification across PVT, statistical design, functional verification and silicon bring up.
• Work closely with layout team to complete the design and oversee the layout quality.
• Develop / drive circuit methodology to achieve the highest design quality metrics.

Skills

ASIC design

Low power design

Machine learning accelerators

Python scripting

Data analysis

Education

Bachelor's degree in Electrical Engineering

Tools

CAD tools

SPICE simulation

CAD automation tools

Digital/mixed-signal design tools

Job description

Apple Inc. is seeking Circuits Engineers to design advanced custom digital megacells for high-performance SOCs. You will develop circuits to improve power efficiency and work with power teams to set specifications.

The role involves SPICE verification, mixed-signal considerations, and silicon bring up, with close collaboration to layout and design teams. A BS and 3+ years in the field are required, with experience in advanced technology nodes and low-power design.