Lead ASIC Verification Engineer — Networking & SoC

Advanced Micro Devices; Santa Clara (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Advanced Micro Devices in Santa Clara seeks a Design Verification Engineer to drive verification closure on complex ASIC designs. The ideal candidate will have expert knowledge in SystemVerilog and UVM, and will work collaboratively across teams to ensure product success.

Responsibilities include developing testbench architectures, executing verification plans, and optimizing methodologies. A Bachelor’s degree in Electrical/Computer Engineering is required, while a Master’s degree is preferred.

Qualifications

• Hands-on verification expertise with high-performance ASIC designs.
• Experience driving verification closure on complex designs.
• Knowledge of industry protocols like PCIe, Ethernet, and DDR.

Responsibilities

• Develop UVM-based testbench architectures for IP and SoC-level verification.
• Own execution of verification plans and debug architectural issues.
• Collaborate with design, validation, and firmware teams.

Skills

Expert-level knowledge of SystemVerilog

Strong hands-on experience with SystemVerilog simulators

Proven experience in verifying complex IP/subsystems

Strong debug skills across architecture, RTL, and testbench layers

Scripting skills in Python, Perl, Shell, Tcl

Education

Bachelor’s Degree in Electrical/Computer Engineering

Master’s Degree

Tools

VCS

Verdi/DVE

Job description

Advanced Micro Devices in Santa Clara seeks a Design Verification Engineer to drive verification closure on complex ASIC designs. The ideal candidate will have expert knowledge in SystemVerilog and UVM, and will work collaboratively across teams to ensure product success.

Responsibilities include developing testbench architectures, executing verification plans, and optimizing methodologies. A Bachelor’s degree in Electrical/Computer Engineering is required, while a Master’s degree is preferred.