Senior ASIC Verification Engineer: SystemVerilog/UVM Lead

NVIDIA Corporation; Austin (TX); On-site; USD 170,000 - 265,000; Full time

Job summary

NVIDIA in Austin, TX is seeking a Senior ASIC Verification Engineer to drive system-level IP verification and robust testbenches. You will design and maintain unit and sub-system verification environments, build UVM components, sequences, tests and scoreboards, and ensure high-quality coverage while collaborating with architects, designers and software engineers.

The role requires a Bachelor’s or Master’s in EE/CS with 3+ years of relevant experience, strong SystemVerilog/UVM and Python skills,

Qualifications

• Bachelor’s or Master’s degree in Computer or Electrical Engineering (or equivalent) with 3+ years of relevant experience.
• Proficient with SystemVerilog, UVM and OOPS based programming; strong RTL design fundamentals.
• Strong Python scripting skills; familiarity with VCS or Verdi debugging tools.

Responsibilities

• Design and maintain unit-level/sub-system verification environments.
• Create UVM components, sequences, tests and scoreboards; sign off with high-quality code and coverage.
• Launch regressions, resolve issues, and push DV milestones forward; automate builds/regression/triage.
• Collaborate with architects, designers, and software engineers to hit project goals.
• Proactively improve testbenches using modern verification techniques.
• Ensure end-to-end verification of IPs with robust, scalable test results.

Skills

SystemVerilog

UVM

Python

Verilog

RTL design

OOP programming

Computer architecture

Education

Bachelor’s or Master’s in Computer or Electrical Engineering

Tools

VCS

Verdi

Job description

NVIDIA in Austin, TX is seeking a Senior ASIC Verification Engineer to drive system-level IP verification and robust testbenches. You will design and maintain unit and sub-system verification environments, build UVM components, sequences, tests and scoreboards, and ensure high-quality coverage while collaborating with architects, designers and software engineers.

The role requires a Bachelor’s or Master’s in EE/CS with 3+ years of relevant experience, strong SystemVerilog/UVM and Python skills,