Senior ASIC Implementation Engineer: Synthesis & Tape-out

Meta; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Silicon Engineering organization in Sunnyvale is seeking a Staff ASIC Implementation Engineer to own end-to-end implementation from RTL to tape-out, driving synthesis, timing closure, and physical design in collaboration with RTL, verification, and architecture teams to deliver high-performance silicon at scale.

The role involves defining reusable flows, creating constraints, mentoring junior engineers, and advancing Meta's custom chip capabilities for AI, data center, and HPC

Qualifications

• 8+ years of experience in ASIC implementation including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs.
• Experience with industry-standard synthesis and implementation EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
• Experience defining and managing synthesis constraints including SDC, UPF, and hierarchical design methodologies

Responsibilities

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, formal verification, and design-for-test integration for complex custom silicon designs
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints that scale across multiple chip projects
• Drive timing closure strategies across hierarchical design partitions, resolving critical path bottlenecks through collaboration with RTL designers and physical design engineers
• Develop and maintain synthesis scripts, constraint files, and automation infrastructure to improve implementation quality and reduce iteration cycles
• Generate SOC floorplans at the chip level, subsystem level, block level and enable block implementation owners to execute on synthesis & physical design
• Perform top-level logical and physical connectivity and beachfront analysis, including pipe/shim and feedthrough block insertion for timing and area optimisation
• Partner with architecture and RTL teams to provide early feedback on design decisions that impact area, power, and timing outcomes
• Define and enforce design rules and quality sign-off criteria across implementation milestones, ensuring readiness for tape-out
• Identify and drive the resolution of cross-functional implementation risks, communicating status and trade-offs to engineering leadership and program stakeholders
• Mentor other engineers on implementation methodology, synthesis best practices, and timing analysis techniques
• Contribute to long-term silicon implementation strategy, evaluating new EDA tools, flows, and technologies to advance Meta's custom chip capabilities

Skills

ASIC implementation

Timing analysis

Scripting Tcl/Python

Synthesis flow design

Mentoring

Education

Bachelor's degree in Computer Science/Engineering or equivalent

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

Job description

Meta's Silicon Engineering organization in Sunnyvale is seeking a Staff ASIC Implementation Engineer to own end-to-end implementation from RTL to tape-out, driving synthesis, timing closure, and physical design in collaboration with RTL, verification, and architecture teams to deliver high-performance silicon at scale.

The role involves defining reusable flows, creating constraints, mentoring junior engineers, and advancing Meta's custom chip capabilities for AI, data center, and HPC