Lead ASIC Design Engineer

Broadcom Inc.; Wayne (CA); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(k) participation with company matching

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom Inc. is seeking a Principal Digital Design Engineer in Wayne, California. In this pivotal role, you will lead the digital architecture for next-generation silicon projects and guide a multi-disciplinary team through the design lifecycle.

You will leverage over 12 years of ASIC/SoC digital design experience, particularly in SystemVerilog/Verilog, to ensure success in each project. The role offers a competitive base salary ranging from $143,800 to $230,000 along with comprehensive benefits.

Qualifications

• 12+ years of direct industry experience in ASIC/SoC digital design.
• Proven history of successful, first-pass silicon tape-outs.
• Must have legal authorization to work in the US.

Responsibilities

• Serve as the Chip Lead for top-level digital architecture.
• Define PPA targets and oversee tape-out sign-off.
• Collaborate with engineering teams across various disciplines.

Skills

Expert-level proficiency in SystemVerilog/Verilog

Knowledge of ASIC/SoC digital design

Outstanding documentation and verbal communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Synthesis tools (e.g., Design Compiler, Genus)

Static Timing Analysis tools (e.g., PrimeTime/Tempus)

Job description

Job Summary

We are seeking a hands‑on Principal Digital Design Engineer to serve as the Chip Lead for our next‑generation silicon projects. In this high‑impact role, you will be the primary technical anchor responsible for the top‑level architecture, microarchitecture, and full chip integration. You will guide a cross‑disciplinary team spanning analog design, physical design, and verification, owning the design outcome end‑to‑end from early product definition to a successful foundry tape‑out.

Leadership & Strategic Responsibilities

• Serve as the central Chip Lead, defining top‑level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
• Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
• Own and drive the final tape‑out sign‑off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
• Provide technical guidance, code reviews, and architectural mentorship to mid‑level and junior engineers on the team.

Technical Execution Responsibilities

• Author, optimize, and maintain high‑quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
• Drive top‑level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block‑level timing budgets for the PD team.
• Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
• Manage the integration of custom internal analog macros, mixed‑signal blocks, and third‑party soft/hard IP.
• Collaborate with post‑silicon validation and software teams during initial chip bring‑up and lab debug phases.

Required Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
• RTL Mastery: Expert‑level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
• Tool Fluency: Deep experience with front‑end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
• Silicon Track Record: Proven history of successful, first‑pass silicon tape‑outs on modern process technologies.
• Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project.
• Work Authorization: Must have legal authorization to work in the US.

Preferred & Bonus Skills

• Experience with mixed‑signal or high‑speed PHY‑adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).
• Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan.
• Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front‑end design flows.

Compensation and Benefits

The annual base salary range for this position is $143,800 - $230,000. You will be eligible for a discretionary annual bonus and opportunities to receive a competitive new‑hire equity grant, annual equity awards, and participation in a comprehensive benefits package including medical, dental, and vision plans, 401(k) participation with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time, and paid family leave.

EEO Statement

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.