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Synopsys, Inc. is seeking an experienced ASIC Digital Architect in Austin to lead RTL design and verification at chip and block levels.
You will define design plans for complex digital designs and focus on high-speed IO protocols such as DDR, PCIe, UCIe, and Ethernet, collaborating with cross-functional teams to ensure integration and performance. You will mentor engineers, apply advanced design methodologies, and communicate with stakeholders to align goals.
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement new HPC Interface IP solutions used by leading semiconductor companies worldwide.
You’ll join a high-impact Synopsys team advancing next-generation design technologies. In this role, you will help shape the architecture and execution of leading digital core protocols—including DDR, PCIe, UCIe and Ethernet technologies—driving innovation, integration, and performance across critical semiconductor solutions.
Synopsys offers a comprehensive package of health, wellness, financial, and professional development benefits designed to support you throughout your career.
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