ASIC Digital Design Engineer, Architect-18709

Synopsys, Inc.; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC Digital Architect to drive the future of semiconductor technology in Austin. You will define and lead RTL design and verification at chip and block levels, shaping architectures for DDR, PCIe, CXL, UAL, and UCIe IO protocols while mentoring junior engineers.

You will collaborate with cross-functional teams to ensure successful integration, apply advanced design methodologies, and influence strategic decisions across Synopsys' digital design efforts.

Qualifications

• Extensive experience in ASIC RTL design.
• Deep knowledge of DDR, PCIe, UAL, UCIe IO protocols.
• Ability to define and execute architecture for protocols like UAL.
• Strong communication and mentoring skills.

Responsibilities

• Define and develop ASIC RTL design and verification at chip and block levels.
• Create and execute design plans for complex digital designs focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
• Collaborate with cross-functional teams for seamless integration.
• Utilize advanced design and verification methodologies to achieve high quality results.
• Mentor junior engineers and promote best practices.

Skills

ASIC RTL design

DDR IO protocols

PCIe/UCIe/UAL

Mentoring

Independent work

Education

BSEE or BSCE +12 years

Advanced degree +10 years

Tools

Advanced digital design tools

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are:

An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

What You’ll Be Doing:

• Defining and developing ASIC RTL design and verification at both chip and block levels.
• Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe, CXL, UAL, UCIe IO protocols.
• Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
• Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
• Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
• Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have:

• Enhancing the reliability and performance of Synopsys' digital design processes.
• Driving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions.
• Improving time-to-market for high-performance silicon chips through efficient methodologies.
• Building and nurturing a highly skilled development team, elevating overall project quality.
• Influencing strategic decisions that shape the future of Synopsys' capabilities.
• Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You’ll Need:

• BSEE or BSCE +12 years or an advanced degree and +10 years industry experience
• Extensive experience in ASIC RTL design.
• In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications.
• Proficiency in advanced digital design tools and methodologies.
• Strong problem-solving skills and the ability to work independently.
• Excellent communication skills for effective collaboration with diverse teams.

Who You Are:

• A visionary leader with a strategic mindset.
• A mentor who fosters talent and encourages innovation.
• A proactive problem solver who thrives in complex environments.
• An effective communicator with the ability to convey technical concepts to a broad audience.
• A team player who values collaboration and diversity.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry. Specifically, according to a match profile, you will be a key technical contributor to the architecture and execution of one of DDR/PCIe/UAL/UCIe digital core protocols.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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