Lead ASIC DFT Engineer – Test & Post-Silicon Debug

Links Technology Solutions, Inc.; Carlsbad (CA); Hybrid; USD 110,000 - 124,000; Full time

Benefits offered by this job

Health insurance

Vision insurance

Dental insurance

Life insurance

401K Matching

Job summary

Links Technology Solutions, Inc. is seeking an ASIC DFT Lead to drive design-for-test features (scan, mbist, BISR, boundary scan) in Carlsbad, CA.

You will lead the development and integration of DFT IP across RTL and post-silicon validation, collaborating with cross-functional teams throughout the silicon lifecycle to ensure high yield and manufacturability. The role requires strong experience with ATPG, Tessent, Xcelium, Genus and temporal primetime, plus mentoring capabilities and excellent

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering required.
• 8–10 years of relevant experience in ASIC DFT.
• Experience with JTAG, Scan, BIST architectures and memory BIST.
• ATPG and EDA tools such as Tessent, Xcelium, Genus, Tempus/Primetime.

Responsibilities

• Implement DFT features such as scan, mbist, BISR, boundary scan and DFT simulations.
• Develop innovative DFT IP and integrate with RTL for full-chip testability.
• Collaborate with multiple teams across the silicon lifecycle.
• Lead debugging and root cause analysis of silicon failures to improve yield and reliability.

Skills

JTAG protocols

Scan & BIST architectures

Memory BIST

Boundary scan

3rd party IPs integration

High speed digital/analog macros

ATPG

EDA tools (Tessent)

Xcelium

Genus

Tempus/Primetime

Post-silicon debug

Team leadership/mentoring

Strong communication

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus/Primetime

Job description

Links Technology Solutions, Inc. is seeking an ASIC DFT Lead to drive design-for-test features (scan, mbist, BISR, boundary scan) in Carlsbad, CA.

You will lead the development and integration of DFT IP across RTL and post-silicon validation, collaborating with cross-functional teams throughout the silicon lifecycle to ensure high yield and manufacturability. The role requires strong experience with ATPG, Tessent, Xcelium, Genus and temporal primetime, plus mentoring capabilities and excellent