Design for Test Lead - ASIC

Links Technology Solutions, Inc.; Carlsbad (CA); Hybrid; USD 110.000 - 124.000; Vollzeit

Benefits dieser Stelle

Health insurance

Vision insurance

Dental insurance

Life insurance

401K Matching

Zusammenfassung

Links Technology Solutions, Inc. is seeking an ASIC DFT Lead to drive design-for-test features (scan, mbist, BISR, boundary scan) in Carlsbad, CA.

You will lead the development and integration of DFT IP across RTL and post-silicon validation, collaborating with cross-functional teams throughout the silicon lifecycle to ensure high yield and manufacturability. The role requires strong experience with ATPG, Tessent, Xcelium, Genus and temporal primetime, plus mentoring capabilities and excellent

Qualifikationen

• Bachelor's or Master's in Electrical or Computer Engineering required.
• 8–10 years of relevant experience in ASIC DFT.
• Experience with JTAG, Scan, BIST architectures and memory BIST.
• ATPG and EDA tools such as Tessent, Xcelium, Genus, Tempus/Primetime.

Aufgaben

• Implement DFT features such as scan, mbist, BISR, boundary scan and DFT simulations.
• Develop innovative DFT IP and integrate with RTL for full-chip testability.
• Collaborate with multiple teams across the silicon lifecycle.
• Lead debugging and root cause analysis of silicon failures to improve yield and reliability.

Kenntnisse

JTAG protocols

Scan & BIST architectures

Memory BIST

Boundary scan

3rd party IPs integration

High speed digital/analog macros

ATPG

EDA tools (Tessent)

Xcelium

Genus

Tempus/Primetime

Post-silicon debug

Team leadership/mentoring

Strong communication

Ausbildung

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus/Primetime

Jobbeschreibung

Title: ASIC Design for Test Lead (DFT)

Location: Carlsbad, CA onsite/hybrid

Pay Rate: $80-$90/HR

Duration: 1 yr extendable

Summary: You will be part of our client's optics development organization as a DFT Technical Lead in Carlsbad, CA with a primary focus on Design-for-Test. You will develop and implement DFT features - ATPG, scan compression, memory BIST, memory repair to ensure high quality testable and manufacturable designs. You will contribute to the full product cycle from pre-silicon design to post-silicon debt and production qualification. You will collaborate across multiple teams throughout the silicon life cycle. Starting from implementing DFT features to lead debugging and root cause analysis of silicon failures to improve yield and reliability. Our chips are strategically placed in AI infrastructure, powering next generation network devices to support advanced AI workloads.

Description – ASIC DFT Lead

• Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
• Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Qualifications – ASIC DFT Lead

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.
• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high speed digital/analog macros.
• Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, Tempus/Primetime.
• At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production.
• Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production.
• Ability to quickly learn new concepts and adapt to evolving technologies.
• Excellent communication and presentation skills.
• Strong attention to detail and system level understanding of networking and photonic solutions.

Benefits:

• $80-$90/hr
• Available health, life, vision, and dental insurance
• 401K Matching
• #IND1