DFT Technical Lead – ASIC Test & Debug

Apex Systems; Carlsbad (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical/dental/vision insurance

401K with company match

ESPP

HSA

EAP with counseling

Certification discounts

Training programs

Job summary

Everforth Apex is seeking a Design for Test- Technical Lead to drive DFT strategy for ASIC projects in Carlsbad, CA or Allentown, PA. You will lead the design-for-test efforts, implement scan, BISR, mbist, and boundary scan, and collaborate across teams to ensure manufacturability and high yield.

You will own post-silicon debug, coordinate with RTL/physical teams, and develop reusable DFT solutions for new silicon devices, with senior leadership and minimal mentorship expectations.

Qualifications

• Bachelors/Masters in EE or CE required.
• 8–10 years' experience with JTAG, Scan, BIST, and 3rd party IP.
• Hands-on post-silicon DFT debug and production release.

Responsibilities

• Implement Hardware Design-for-Test (DFT) features: scan, mbist, BISR, boundary scan.
• Set up and debug DFT simulations; support post-silicon testing and debug.
• Develop DFT IP and integrate testability into RTL.
• Collaborate on HW DFT and physical design aspects for new silicon models.
• Drive reusable test and debug strategies for bare die and stacked die.
• Craft solutions and debug with minimal mentorship.

Skills

JTAG protocols

DFT

ATPG

Boundary scan

MBIST

Memory BIST

3rd party IP integration

High-speed digital/analog macros

Post-silicon debug

RTL testability integration

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus/Primetime

Job description

Everforth Apex is seeking a Design for Test- Technical Lead to drive DFT strategy for ASIC projects in Carlsbad, CA or Allentown, PA. You will lead the design-for-test efforts, implement scan, BISR, mbist, and boundary scan, and collaborate across teams to ensure manufacturability and high yield.

You will own post-silicon debug, coordinate with RTL/physical teams, and develop reusable DFT solutions for new silicon devices, with senior leadership and minimal mentorship expectations.