Consulting Engineer 3: 26-02765

Akraya; Carlsbad (CA); On-site; USD 96,000 - 103,000; Full time

Job summary

Akraya, Inc. is seeking two lead-caliber ASIC DFT engineers in Carlsbad, CA with remote option.

You will design and implement advanced DFT features for silicon devices powering AI workloads, ensuring testable and manufacturable designs from pre-silicon to post-silicon qualification. Collaborate across RTL, EDA, and test teams to implement scan, MBIST, BIST, boundary scan; debug DFT simulations; support post-silicon testing and production release.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 8–10 years of ASIC DFT experience.
• Proficient in JTAG, Scan, and BIST architectures including MBIST.
• Experience with ATPG and EDA tools (Tessent, Xcelium, Genus, Tempus/Primetime).
• Hands-on post-silicon DFT debugging and production release experience.

Responsibilities

• Implement DFT features: scan, MBIST, BIST, boundary scan.
• Set up and debug DFT simulations and support post-silicon testing.
• Collaborate with RTL, IP, and test teams to integrate testability at RTL.
• Develop hardware DFT and physical design for new silicon models (bare die).
• Craft independent, mentorship-light problem-solving for complex issues.

Skills

ASIC DFT

JTAG/Scan/BIST Architectures

ATPG & EDA Tools

Post-Silicon Debug

RTL Integration

Education

Bachelor's or Master's Degree in Electrical or Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus/Primetime

Job description

Primary Skills: ASIC DFT (Expert), JTAG/Scan/BIST Architectures (Advanced), ATPG & EDA Tools (Advanced), Post-Silicon Debug (Advanced), RTL Integration (Intermediate) Contract Type: W2 Only Duration: 12+ Months (Possible extension) Location: Carlsbad, CA (Remote | PST hours) Pay Range: $70-$75/hr on W2

Job Summary

This is a critical contract opportunity for two lead-caliber ASIC DFT experienced engineers. You will play a pivotal role in designing and implementing advanced Design-for-Test (DFT) features for our cutting-edge silicon devices, powering next‑generation network devices for advanced AI workloads. You will be instrumental in ensuring high-quality, testable, and manufacturable designs throughout the full product cycle, from pre-silicon design through post-silicon debug and production qualification.

Key Responsibilities

• Implement hardware Design-for-Test (DFT) features including scan, Memory BIST (MBIST), Built-In Self-Test (BIST), and boundary scan.
• Set up and debug DFT simulations, and provide essential support for post-silicon testing and debug.
• Collaborate with multi-functional teams to develop innovative DFT Intellectual Property (IP) and integrate testability features at the RTL level.
• Create innovative hardware DFT and physical design aspects for new silicon device models (bare die & stacked die), driving reusable test and debug strategies.
• Independently craft solutions and debug complex issues with minimal mentorship.

Must-Have Skills

• Bachelor's or Master's Degree in Electrical or Computer Engineering, with at least 8-10 years of relevant ASIC DFT experience.
• Proficient in JTAG protocols, Scan and BIST architectures (including Memory BIST), and integrating third-party IPs and high-speed digital/analog macros.
• Experience with ATPG (Automated Test Pattern Generation) and EDA tools such as Tessent tool sets, Xcelium, Genus, and Tempus/Primetime.
• At least one project with hands‑on post-silicon debug of DFT patterns (scan, MBIST, boundary scan) and successful release to production.
• Ability to work independently and debug with minimal mentorship.

Industry Experience

Semiconductor Industry (ASIC Design) Experience in networking and photonic solutions is a plus.