DFT Lead

Avicena Tech; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Avicena Tech is seeking a DFT Lead to own the test architecture of a mixed-signal ASIC, from scan and BIST through analog test access and production test delivery. You will define the strategy, implement and verify it, and collaborate with product/test engineering to bring it up on the tester.

You will drive DFT features, ensure coverage and timing targets, and coordinate with design teams. This role requires 10+ years in DFT on production ASICs and hands-on experience with Tessent/Synopsys

Qualifications

• BS or MS in Electrical or Computer Engineering with 10+ years of DFT experience on production ASICs.
• Hands-on expertise with Siemens Tessent or Synopsys TestMAX/DFTMAX/TetraMAX.
• Scan compression, ATPG, memory BIST and JTAG/IJTAG.
• Gate-level simulation of test patterns and test-mode timing closure.
• ATE bring-up and silicon failure diagnosis.

Responsibilities

• Own the DFT architecture and strategy for a mixed-signal ASIC, including coverage and test-time targets.
• Implement scan insertion and compression, and generate ATPG patterns for stuck-at, transition and path-delay faults.
• Implement memory BIST and repair, and IEEE 1149.1/1687 access for test and instrument control.
• Define link-level test features with the design teams: loopback modes, PRBS generators and checkers, and analog observability and trim access.
• Verify DFT logic and patterns with gate-level simulation, and close test-mode timing with the implementation team.
• Deliver ATE patterns and support tester bring-up with product/test engineering.
• Diagnose silicon failures and support yield learning and test-time reduction.
• Grow DFT capability as the team expands.

Skills

DFT leadership

Gate-level simulation

ATE bring-up

Education

BS or MS in Electrical or Computer Engineering

Tools

Siemens Tessent

Synopsys TestMAX

DFTMAX

TetraMAX

JTAG

Memory BIST

Job description

About The Role

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a DFT Lead to own the test architecture of our mixed-signal ASIC, from scan and BIST through analog test access and production test delivery. You will define the strategy, implement and verify it, and work with product/test engineering to bring it up on the tester.

Job Title

DFT Lead

Key Responsibilities

• Own the DFT architecture and strategy for a mixed-signal ASIC, including coverage and test-time targets.
• Implement scan insertion and compression, and generate ATPG patterns for stuck-at, transition and path-delay faults.
• Implement memory BIST and repair, and IEEE 1149.1/1687 access for test and instrument control.
• Define link-level test features with the design teams: loopback modes, PRBS generators and checkers, and analog observability and trim access.
• Verify DFT logic and patterns with gate-level simulation, and close test-mode timing with the implementation team.
• Deliver ATE patterns and support tester bring-up with product/test engineering.
• Diagnose silicon failures and support yield learning and test-time reduction.
• Grow DFT capability as the team expands.

Qualifications

Required

• BS or MS in Electrical or Computer Engineering with 10+ years of DFT experience on production ASICs.
• Hands‑on expertise with Siemens Tessent or Synopsys TestMAX/DFTMAX/TetraMAX.
• Scan compression, ATPG, memory BIST and JTAG/IJTAG.
• Gate‑level simulation of test patterns and test‑mode timing closure.
• ATE bring‑up and silicon failure diagnosis.

Preferred

• DFT for mixed‑signal chips with analog test access.
• Test of high‑speed I/O, including loopback, PRBS and margining; IEEE 1149.6.
• Hierarchical DFT.
• Yield analysis and diagnosis tools.
• Experience leading DFT engineers.

Key Competencies

• Ownership: accountable for test quality from architecture to production.
• Pragmatic: balances coverage, area and test time.
• Collaboration: works across design, implementation and test engineering.
• Problem solver: methodical in silicon debug.