ASIC Design Engineer

Anysilicon; Sunnyvale (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Hewlett Packard Enterprise (HPE) in Sunnyvale, CA, is seeking an ASIC Design Engineer to join its Networking Silicon group. This onsite role emphasizes collaboration and innovation in a fast-paced environment.

You will develop micro-architecture specs, write SVAs, and work with Physical Design and Verification teams. The ideal candidate has a BS in EE with 3–4+ years of experience, strong analytical and problem-solving skills, and proficiency in Verilog/SystemVerilog.

Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred) with 3-4+ years of relevant experience.
• Strong analytical and problem-solving skills.
• Knowledge of computer architecture and networking protocols is a plus.
• Proficient coding skills in Verilog/SystemVerilog.
• Familiarity with synthesis, lint, and other EDA tools is desired.

Responsibilities

• Develop micro-architecture specifications from functional specs meeting power/area targets.
• Write functional coverage and SystemVerilog Assertions (SVA) for verification.
• Collaborate with Physical Design for floorplan and timing closure.
• Work with Verification to validate design blocks.
• Mentor and guide new graduates and interns.

Skills

Verilog/SystemVerilog

Perl/Python

Analytical thinking

Problem solving

Agile/Scrum

Cross-functional teamwork

Data analysis

Communication skills

Education

Bachelor’s in Electrical Engineering

Master’s preferred

Tools

Synthesis tools

Lint tools

EDA tools

Job description

Job Description:

Hewlett Packard Enterprise (HPE) is seeking an ASIC Design Engineer to join its Networking Silicon group, which specializes in advanced networking chips for routers and switches. This role is primarily onsite at an HPE office, emphasizing collaboration and innovation in a fast-paced environment. HPE values diverse backgrounds and offers opportunities for personal and professional growth.

Responsibilities:

• Develop detailed micro-architecture specifications from functional specifications that meet power and area requirements.


• Write functional coverage and SystemVerilog Assertions (SVA) to assist in verification and catch corner case bugs.


• Collaborate with the Physical Design team for optimal floorplan and timing closure, identifying and fixing timing issues in RTL to meet frequency targets.


• Work with the Verification team to ensure full validation of design blocks.


• Mentor and guide new college graduates and interns to enhance leadership skills.

Qualifications:

• Bachelor’s degree in Electrical Engineering (Master’s preferred) with 3-4+ years of relevant experience.


• Strong analytical and problem-solving skills.


• Knowledge of computer architecture and networking protocols is a plus.


• Proficient coding skills in Verilog/System Verilog from coursework or prior experience.


• Familiarity with synthesis, lint, and other EDA tools is desired.

Skills:

• Excellent written and verbal communication skills.


• Knowledge of Perl/Python is a plus.


• Accountability and action planning.


• Active learning and listening skills.


• Agile methodology and Scrum development experience.


• Analytical thinking and creativity.


• Cross-functional teamwork and data analysis management.