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Hewlett Packard Enterprise Development LP in Roseville, California, seeks a Sr. ASIC Design Engineer to drive high‑speed networking chips from specifications to final netlist. You will work with verification, physical design, and leadership to deliver robust, efficient silicon in a hybrid office model.
The role emphasizes Verilog/SystemVerilog design, RTL timing, and collaboration with cross‑functional teams; strong communication and problem‑solving are essential.
Hewlett Packard Enterprise Development LP in Roseville, California, seeks a Sr. ASIC Design Engineer to drive high‑speed networking chips from specifications to final netlist. You will work with verification, physical design, and leadership to deliver robust, efficient silicon in a hybrid office model.
The role emphasizes Verilog/SystemVerilog design, RTL timing, and collaboration with cross‑functional teams; strong communication and problem‑solving are essential.