Senior ASIC Design Engineer — High‑Speed Networking (Hybrid)

Hewlett Packard Enterprise

Roseville (CA)

Hybrid

USD 159,000 - 321,000

Full time

10 days ago

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Benefits offered by this job

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Job summary

Hewlett Packard Enterprise Development LP in Roseville, California, seeks a Sr. ASIC Design Engineer to drive high‑speed networking chips from specifications to final netlist. You will work with verification, physical design, and leadership to deliver robust, efficient silicon in a hybrid office model.

The role emphasizes Verilog/SystemVerilog design, RTL timing, and collaboration with cross‑functional teams; strong communication and problem‑solving are essential.

Qualifications

  • Bachelor’s degree in Electrical Engineering with 5+ years of relevant experience.
  • Strong knowledge of Verilog/SystemVerilog and RTL design.
  • Experience with synthesis, lint and state-of-the-art EDA tools.
  • Excellent written and verbal communication skills.

Responsibilities

  • Start with a functional specification of a module and produce a detailed micro-architecture specification.
  • Implement the design using Verilog or SystemVerilog and verify thoroughly.
  • Collaborate with Physical Design for timing closure and floorplanning.
  • Mentor new engineers and interns as needed.

Skills

Strong analytical
Problem solving
Excellent communication
AI tools experience

Education

Bachelor's degree in Electrical Engineering
Master's degree strongly desired

Tools

Verilog/SystemVerilog
EDA tools
Synthesis / lint
Perl / Python

Job description

Hewlett Packard Enterprise Development LP in Roseville, California, seeks a Sr. ASIC Design Engineer to drive high‑speed networking chips from specifications to final netlist. You will work with verification, physical design, and leadership to deliver robust, efficient silicon in a hybrid office model.

The role emphasizes Verilog/SystemVerilog design, RTL timing, and collaboration with cross‑functional teams; strong communication and problem‑solving are essential.

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