Lead Analog Layout Architect – High-Speed Optics

Cisco Systems; Allentown (Lehigh County); On-site; USD 149,000 - 218,000; Full time

Job summary

Cisco Systems is seeking a Senior Analog Layout Engineer for the Silicon One Optics team in the United States. You will architect the physical blueprint for high-speed optical interconnects and own block-to-top integration for 100G–400G lambda designs, from floorplanning to tapeout and bring-up.

Collaborate with CAD, circuit design, and packaging teams to manage parasitic control, signal integrity, and thermal tradeoffs, mentoring engineers and advancing design methodologies across the group.

Qualifications

• Minimum Qualifications include: Bachelor s degree with 7+ years related experience, or Master s degree with 4+ years related experience, or PhD with 1+ year related experience
• Experience supporting block-level layout through tapeout
• Experience in physical verification and custom layout design, especially with FINFET 7nm/5nm/3nm
• Experience with Cadence Virtuoso or similar custom layout tools

Responsibilities

• Own block-to-top integration for next-gen 100G, 200G and 400G lambda architectures from floorplanning to tapeout and bring-up
• Directly build and optimize analog and mixed-signal layouts for 100G–400G optical solutions
• Collaborate with cross-functional teams on parasitic control, SI, and thermal tradeoffs
• Mentor rising engineering talent and help shape design methodologies across the group

Skills

Analog & Custom Layout Design

Parasitic control

Thermal management

Signal integrity

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Calibre

Job description

Cisco Systems is seeking a Senior Analog Layout Engineer for the Silicon One Optics team in the United States. You will architect the physical blueprint for high-speed optical interconnects and own block-to-top integration for 100G–400G lambda designs, from floorplanning to tapeout and bring-up.

Collaborate with CAD, circuit design, and packaging teams to manage parasitic control, signal integrity, and thermal tradeoffs, mentoring engineers and advancing design methodologies across the group.