Senior High-Speed Analog Layout Engineer — Cut-Edge IP

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive layout of ADCs, DACs, PLLs and other high-performance blocks for optical communication systems.

You will lead the AMS layout team, mentor engineers across time zones, and collaborate with circuit designers to ensure first-pass silicon success. The role requires extensive hands-on experience in analog/mixed-signal layouts,Cadence Virtuoso and Calibre, and familiarity with top-level integration and

Qualifications

• 10+ years hands-on analog/mixed-signal layout experience in advanced CMOS/FinFET tech
• Proven track record in IP/layout macros or full-chip layout
• Leadership in owning major IP layout macros or full-chip layouts at FinFET nodes (TSMC preferred)
• Experience with TSMC FinFET nodes (N3,N5,N7,N16)
• Strong understanding of LOD, WPE, OSE, LDE and related effects on performance
• Expertise in floor planning, hierarchical integration, routing and power/ground design
• Familiarity with LVS, DRC, PERC, Density, DFM, ERC, Antenna rules

Responsibilities

• Lead physical layout design of analog/mixed-signal macros from floor planning to final verification
• Collaborate with schematic designers to optimize layout for performance and reliability
• Mentor junior layout engineers across time zones following best practices
• Perform and debug LVS, DRC, PERC, ERC using Pegasus, Calibre, etc.
• Contribute to chip-level planning including top-level floor planning and power grid design
• Lead layout design reviews and ensure quality, verification, and schedule adherence
• Support automation through scripting (SKILL, TCL, Python)

Skills

Analog/mixed-signal layout

Leadership

Mentoring

Layout verification

Schematic interaction

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive layout of ADCs, DACs, PLLs and other high-performance blocks for optical communication systems.

You will lead the AMS layout team, mentor engineers across time zones, and collaborate with circuit designers to ensure first-pass silicon success. The role requires extensive hands-on experience in analog/mixed-signal layouts,Cadence Virtuoso and Calibre, and familiarity with top-level integration and