Lead High-Speed Analog Layout Architect

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Senior/Principal Analog Layout Engineer to drive the layout of complex IP blocks (ADCs, DACs, PLLs) for high-performance optical communication systems.

You will lead layout development, collaborate with circuit designers, and mentor junior engineers across time zones. The role involves hands-on layout in advanced CMOS/FinFET processes, top-level planning, and verification using industry tools.

Qualifications

• 10+ years in analog/mixed-signal layout in CMOS/FinFET.
• Experience delivering IP layout macros and handoff to Physical Design.
• Strong collaboration across international teams and mentoring responsibilities.

Responsibilities

• Lead and own physical layout of analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers to optimize performance, matching, symmetry.
• Mentor junior layout engineers and contractors across time zones.
• Perform LVS/DRC/PERC/ERC and other checks using industry tools.
• Contribute to chip-level planning, floor planning, power grid, and routing.
• Participate in layout design reviews and drive quality and schedule adherence.
• Support automation through scripting (SKILL, TCL, Python).

Skills

Analog/mixed-signal layout

CMOS/FinFET layout

LVS/DRC/PERC/ERC

Cadence Virtuoso

Calibre

Pegasus

Leadership/mentoring

Scripting (Python/TCL)

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communications, Inc. is seeking a Senior/Principal Analog Layout Engineer to drive the layout of complex IP blocks (ADCs, DACs, PLLs) for high-performance optical communication systems.

You will lead layout development, collaborate with circuit designers, and mentor junior engineers across time zones. The role involves hands-on layout in advanced CMOS/FinFET processes, top-level planning, and verification using industry tools.