Digital ASIC Design Leader - 100/200/400G Silicon

Cisco; Carlsbad (CA); On-site; USD 178,000 - 257,000; Full time

Job summary

Cisco is seeking a Digital Design Technical Leader for Silicon One Optics in the U.S. You will own the full ASIC lifecycle from concept to tape‑out, leading cross‑functional teams across digital, analog, firmware and physical design to deliver next‑gen high‑speed interconnects.

Define architectures, integrate SerDes/PHY IP, and optimize power and performance for 100G–400G silicon photonics. This role requires 6+ years of leadership and deep ASIC experience.

Qualifications

• Must-have advanced digital design experience across FSMs, CPU subsystems and complex SoCs.
• Experience managing full ASIC/SoC design flow from concept to tape-out.
• Proficiency with high-speed IPs, SerDes, Ethernet and D2D PHY IP.

Responsibilities

• Own the full ASIC lifecycle from concept to post-silicon production.
• Lead cross-functional teams across digital, analog, firmware and physical design.
• Define digital architectures and integrate high-speed IPs for 100G–400G.
• Optimize power, performance and area for silicon photonics and Co-Packaged Optics.

Skills

FSMs

CPU subsystems

Complex SoCs

FPGA validation

ASIC/SoC design flow

SPI/I2C/APB/AXI

High-speed SerDes

Ethernet IP

D2D PHY IP

End-to-End Silicon Lifecycle & Arch

Specification & Microarchitecture

Verification & IP Integration

Implementation & Backend

Technical Leadership

Education

Bachelor's + 12 years

Master's + 8 years

PhD + 5 years

Job description

Cisco is seeking a Digital Design Technical Leader for Silicon One Optics in the U.S. You will own the full ASIC lifecycle from concept to tape‑out, leading cross‑functional teams across digital, analog, firmware and physical design to deliver next‑gen high‑speed interconnects.

Define architectures, integrate SerDes/PHY IP, and optimize power and performance for 100G–400G silicon photonics. This role requires 6+ years of leadership and deep ASIC experience.