Lead AI Processor Architect for Next-Gen Inference ASIC

European Tech Recruit

San Francisco (CA)

Sur place

USD 250 000 - 420 000

Plein temps

Il y a 7 heures
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Résumé du poste

European Tech Recruit is seeking a Senior Principal ASIC Architect to drive the architectural planning of next-generation AI processors. You will define chip-to-chip networking, including HBM and PCIe, and map AI workloads to hardware through detailed modelling and RTL verification.

You will mentor teams, coordinate with external partners, and establish major ASIC milestones to ensure peak performance, power efficiency, and manufacturability for hyperscale data center deployments.

Qualifications

  • 15+ years hands-on silicon design engineering experience.
  • Deep expertise in HBM and high-speed SerDes networking.
  • Strong understanding of generative AI algorithms and transformer models.

Responsabilités

  • Lead architectural planning for next-gen AI processors.
  • Define chip-to-chip networking fabrics including HBM and PCIe.
  • Analyse requirements and propose silicon solutions.
  • Develop detailed design specs and lead modelling activities.
  • Establish ASIC milestones ensuring functionality and efficiency.
  • Collaborate with external partners and cross-functional teams.
  • Provide technical guidance and mentor engineering teams.
  • Evaluate silicon IP, EDA tools and design methodologies.

Connaissances

Silicon design
Architectural planning
RTL verification
Performance modelling
SystemC/TLM
Python scripting
C/C++
Verilog
EDA tools
HBM/SerDes

Outils

Verilog
RTL Design
SystemC
TLM
Python
Perl

Description du poste

European Tech Recruit is seeking a Senior Principal ASIC Architect to drive the architectural planning of next-generation AI processors. You will define chip-to-chip networking, including HBM and PCIe, and map AI workloads to hardware through detailed modelling and RTL verification.

You will mentor teams, coordinate with external partners, and establish major ASIC milestones to ensure peak performance, power efficiency, and manufacturability for hyperscale data center deployments.

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