Principal Design Engineer - AI/HPC Network ASIC Lead

Credo; Pittsburgh (Allegheny County); Sur place; USD 144 000 - 228 000; Plein temps

Avantages offerts par ce poste

Discretionary bonus

Equity

Medical benefits

Résumé du poste

Credo is seeking a principal technical leader to drive hands-on digital ASIC design and strategic architecture for its High‑Performance Network Interface IP portfolio. The role influences interconnect infrastructure for AI and HPC, with potential focus on RTL execution or architecture planning.

The ideal candidate has deep expertise in memory subsystems, Ethernet, PCIe, CXL, UCIe, and related interconnects, and can shape product roadmaps, requirements, and long‑range technology investments

Qualifications

• Eight+ years of experience with technical leadership in electrical engineering or computer engineering.
• Digital design expertise (state machines, data paths, FIFOs, clock/reset) targeting deep sub-micron nodes.
• Deep knowledge of Ethernet, PCIe, CXL, UCIe, UALink, and related standards.
• Strong systems thinking with ability to translate tradeoffs into product direction and requirements.
• Advanced debugging and Unix/Linux scripting; experience with industry EDA tools.

Responsabilités

• Lead RFQ evaluations and guide tradeoffs across functionality, power, performance, and area.
• Define product and technology roadmaps based on customer needs and market direction.
• Own scoping and execution tracking of design activities and releases, with clear documentation.
• Develop, debug, and enhance RTL; perform synthesis tasks and support verification; lead design reviews.
• Identify risks and align cross‑team stakeholders on priorities and strategy.

Connaissances

Digital design

Verilog/SystemVerilog

Networking protocols

Unix/Linux scripting

Cadence/Mentor/Synopsys tools

Formation

BS/MS in Electrical or Computer Engineering

Outils

Cadence

Mentor

Synopsys

Description du poste

Credo is seeking a principal technical leader to drive hands-on digital ASIC design and strategic architecture for its High‑Performance Network Interface IP portfolio. The role influences interconnect infrastructure for AI and HPC, with potential focus on RTL execution or architecture planning.

The ideal candidate has deep expertise in memory subsystems, Ethernet, PCIe, CXL, UCIe, and related interconnects, and can shape product roadmaps, requirements, and long‑range technology investments