Principal ASIC Architect

USA Tech Recruit; United States; À distance; USD 180 000 - 280 000; Plein temps

Résumé du poste

USA Tech Recruit is seeking a Principal ASIC Architect to lead architecture definition and design for its next-generation AI inference processors. Based in the San Francisco Bay Area with remote options, the role blends high-level silicon planning with hands-on design and mentoring across teams.

You will drive IP evaluation, RTL verification, performance modelling and collaboration with external partners and internal engineers to deliver scalable, power-efficient accelerator silicon for data

Qualifications

• 15+ years of hands-on experience in silicon design and architectural planning of HPC processors and AI workloads.
• Strong understanding of generative AI algorithms and mapping to hardware.
• Excellent Verilog, RTL verification and performance modelling.
• Proficient in C/C++ and scripting languages (Python, Perl) for automation.
• MS or PhD in Electrical/Computer Engineering or related field.

Responsabilités

• Lead architectural planning and definition of AI processors with high-performance compute cores, memory, and interconnects.
• Define design specifications, modelling, and milestones to ensure functionality, performance and manufacturability.
• Collaborate with external partners, design and verification teams, and product management; provide technical guidance and reviews.
• Evaluate silicon IP, EDA tools and methodologies to improve design efficiency and outcomes.

Connaissances

Silicon design engineering

Architectural planning

HPC processors

HBM & SerDes

Verilog

RTL verification

Performance modelling

C/C++

Python or Perl

MS/PhD EE/CE

Formation

MS in Electrical Engineering

PhD in Electrical Engineering

Outils

SystemC

TLM

C-models

EDA tools

Description du poste

A well-funded, fast-paced AI start-up is building very high-performance, low-power generative AI inference systems. Combining custom silicon, hardware and software, the company delivers multimodal generative AI inference acceleration at scale for hyperscaler and neocloud data center customers. The team is based in the San Francisco Bay Area, with additional members working remotely across North America and Europe.

The company is seeking a Principal ASIC Architect to lead all phases of ASIC architecture definition and design for its next-generation family of processors for generative AI inference acceleration. HQ'd in the San Francisco Bay Area, California, this is an exciting opportunity that combines high-level silicon architecture planning, hands-on design, prototyping of ASIC design concepts, mentoring and technical leadership. You will help deliver the high-performance, multi-chip silicon solutions at the heart of the company’s vertically integrated generative AI inference acceleration systems for data centers.

This can either be onsite in Sunnyvale or fully remote in the US.

Key Responsibilities:

• Lead the architectural planning and definition of new AI processors featuring highly specialised floating-point AI compute cores, embedded memory, embedded RISC-V CPU cores, and high-speed serial communications with a chip-to-chip networking fabric, HBM and PCIe connectivity.
• Analyse technical needs, propose chip design solutions, produce detailed design specifications, lead architectural modelling and set ASIC development milestones to ensure the final product meets requirements for functionality, inference performance, inference accuracy, power efficiency, programmability, debuggability and manufacturability.
• Work closely with external engineering partners, ASIC design engineers, ASIC design verification teams, SoC physical design teams, interdisciplinary software teams, product management and executives, providing technical guidance, overseeing design reviews and mentoring where applicable.
• Lead the evaluation of new silicon IP technologies, EDA tools and methodologies to enhance the product and improve the efficiency of the chip design process.

Key Qualifications:

• 15+ years of hands-on experience and deep expertise in silicon design engineering and architectural planning of high-performance compute (HPC) processors such as GPUs, CPUs and TPUs, as well as HBM and high-speed SerDes networking technologies for AI workloads.
• Strong understanding of generative AI algorithms, attention mechanisms and foundation transformer models, and of how to map these functions to hardware.
• Strong Verilog programming skills, with experience in RTL verification and performance modelling. Experience in performance analysis, debugging and optimisation is also required.
• Proven track record of developing architectural C-models, SystemC or TLM, with expert-level skills in C/C++ and scripting languages such as Python or Perl for automation and modelling.
• MS or PhD in Electrical Engineering, Computer Engineering or a related engineering discipline.

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