Principal ASIC Architect

European Tech Recruit; San Francisco (CA); Sur place; USD 250 000 - 420 000; Plein temps

Résumé du poste

European Tech Recruit is seeking a Senior Principal ASIC Architect to drive the architectural planning of next-generation AI processors. You will define chip-to-chip networking, including HBM and PCIe, and map AI workloads to hardware through detailed modelling and RTL verification.

You will mentor teams, coordinate with external partners, and establish major ASIC milestones to ensure peak performance, power efficiency, and manufacturability for hyperscale data center deployments.

Qualifications

• 15+ years hands-on silicon design engineering experience.
• Deep expertise in HBM and high-speed SerDes networking.
• Strong understanding of generative AI algorithms and transformer models.

Responsabilités

• Lead architectural planning for next-gen AI processors.
• Define chip-to-chip networking fabrics including HBM and PCIe.
• Analyse requirements and propose silicon solutions.
• Develop detailed design specs and lead modelling activities.
• Establish ASIC milestones ensuring functionality and efficiency.
• Collaborate with external partners and cross-functional teams.
• Provide technical guidance and mentor engineering teams.
• Evaluate silicon IP, EDA tools and design methodologies.

Connaissances

Silicon design

Architectural planning

RTL verification

Performance modelling

SystemC/TLM

Python scripting

C/C++

Verilog

EDA tools

HBM/SerDes

Outils

Verilog

RTL Design

SystemC

TLM

Python

Perl

Description du poste

We are currently partnered with a well-funded, fast-growing AI technology organisation developing high-performance, low-power generative AI inference systems. The company combines custom silicon, hardware and software to accelerate multimodal AI inference for hyperscale and neocloud data centre customers. This senior technical leadership opportunity focuses on the architecture and design of next-generation AI processors, combining high-level silicon architecture planning with hands-on design, modelling and prototyping.

Key responsibilities

• Lead the architectural planning and definition of next-generation AI processors incorporating specialised floating-point compute cores, embedded memory, RISC-V CPU cores and high-speed serial communications.
• Define chip-to-chip networking fabrics and connectivity solutions incorporating HBM and PCIe.
• Analyse technical requirements and propose silicon architecture and design solutions.
• Develop detailed design specifications and lead architectural modelling activities.
• Establish ASIC development milestones and ensure designs meet requirements for functionality, inference performance, accuracy, power efficiency, programmability, debuggability and manufacturability.
• Work closely with external engineering partners, ASIC design and verification teams, SoC physical design teams, software teams, product management and executive stakeholders.
• Provide technical guidance, oversee design reviews and mentor engineering teams.
• Lead the evaluation of new silicon IP technologies, EDA tools and design methodologies to improve product capabilities and chip development efficiency.

Key requirements

• 15+ years' hands-on experience in silicon design engineering and architectural planning for high-performance computing processors, including GPUs, CPUs or TPUs.
• Deep expertise in HBM and high-speed SerDes networking technologies for AI workloads.
• Strong understanding of generative AI algorithms, attention mechanisms and foundation transformer models, including mapping these workloads to hardware.
• Experience with RTL verification and performance modelling.
• Experience in performance analysis, debugging and optimisation.
• Track record of developing architectural C-models, SystemC or Transaction-Level Models (TLM).
• Proficiency in scripting languages such as Python or Perl for automation and modelling.

Keywords

Principal ASIC Architect / ASIC Architecture / Silicon Architecture / AI Processor Architecture / High-Performance Computing / HPC / GPU / CPU / TPU / AI Accelerators / Generative AI / AI Inference / Transformer Models / Foundation Models / Attention Mechanisms / Floating-Point Compute / RISC-V / Embedded CPU / Embedded Memory / HBM / High Bandwidth Memory / SerDes / High-Speed Networking / Chip-to-Chip Interconnect / Networking Fabric / PCIe / Verilog / RTL Design / RTL Verification / Performance Modelling / Architectural Modelling / C-Models / SystemC / TLM / C / C++ / Python / Perl / EDA Tools / Silicon IP / ASIC Development / Power Efficiency / Inference Performance / Technical Leadership / Design Reviews

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