Principal ASIC Architect - Generative AI Processor (Remote)

USA Tech Recruit; United States; À distance; USD 180 000 - 280 000; Plein temps

Résumé du poste

USA Tech Recruit is seeking a Principal ASIC Architect to lead architecture definition and design for its next-generation AI inference processors. Based in the San Francisco Bay Area with remote options, the role blends high-level silicon planning with hands-on design and mentoring across teams.

You will drive IP evaluation, RTL verification, performance modelling and collaboration with external partners and internal engineers to deliver scalable, power-efficient accelerator silicon for data

Qualifications

• 15+ years of hands-on experience in silicon design and architectural planning of HPC processors and AI workloads.
• Strong understanding of generative AI algorithms and mapping to hardware.
• Excellent Verilog, RTL verification and performance modelling.
• Proficient in C/C++ and scripting languages (Python, Perl) for automation.
• MS or PhD in Electrical/Computer Engineering or related field.

Responsabilités

• Lead architectural planning and definition of AI processors with high-performance compute cores, memory, and interconnects.
• Define design specifications, modelling, and milestones to ensure functionality, performance and manufacturability.
• Collaborate with external partners, design and verification teams, and product management; provide technical guidance and reviews.
• Evaluate silicon IP, EDA tools and methodologies to improve design efficiency and outcomes.

Connaissances

Silicon design engineering

Architectural planning

HPC processors

HBM & SerDes

Verilog

RTL verification

Performance modelling

C/C++

Python or Perl

MS/PhD EE/CE

Formation

MS in Electrical Engineering

PhD in Electrical Engineering

Outils

SystemC

TLM

C-models

EDA tools

Description du poste

USA Tech Recruit is seeking a Principal ASIC Architect to lead architecture definition and design for its next-generation AI inference processors. Based in the San Francisco Bay Area with remote options, the role blends high-level silicon planning with hands-on design and mentoring across teams.

You will drive IP evaluation, RTL verification, performance modelling and collaboration with external partners and internal engineers to deliver scalable, power-efficient accelerator silicon for data