ASIC Verification Engineer I — Shape AI-Scale Data Centers

Cisco Systems, Inc; San Jose (CA); On-site; USD 108,000 - 157,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Parental leave

Disability insurance

Life insurance

Paid holidays and vacation time

Job summary

Cisco Systems, Inc is seeking an ASIC Engineer to advance verification for cutting‑edge data center solutions. You will work with verification engineers, designers, and hardware teams to verify ASICs in simulation, emulation, and bring‑up to ensure performance and integration with Cisco hardware platforms.

The role emphasizes maintaining DV environments, building test benches, and delivering thorough test plans and coverage. Strong SystemVerilog/UVM and scripting skills are required.

Qualifications

• Bachelor's degree in ASIC Design/Verification or related field required.
• Experience in ASIC Design/Verification fields preferred.
• Knowledge of SystemVerilog/UVM and scripting languages (Perl/Python) required.

Responsibilities

• Maintain and enhance existing DV environments.
• Construct test benches with scoreboard, agents, sequencers, monitors.
• Write test plans, develop test cases, debug regressions, drive verification closure.
• Ensure complete verification coverage through code and functional coverage reviews.

Skills

Cross-functional collaboration

Verbal communication

Written communication

Education

Bachelor's degree in ASIC Design/Verification or related field

Engineering degree (Electrical/Computer)

Tools

SystemVerilog

UVM

Perl

Python

Job description

Cisco Systems, Inc is seeking an ASIC Engineer to advance verification for cutting‑edge data center solutions. You will work with verification engineers, designers, and hardware teams to verify ASICs in simulation, emulation, and bring‑up to ensure performance and integration with Cisco hardware platforms.

The role emphasizes maintaining DV environments, building test benches, and delivering thorough test plans and coverage. Strong SystemVerilog/UVM and scripting skills are required.