Junior ASIC Verification Engineer — UVM & SystemVerilog

Anysilicon; Austin (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

NVIDIA in Austin, TX is seeking an entry-level ASIC Verification Engineer to join our SOC group. You will help design and verify unit and sub-system blocks, build verification environments, and contribute to IP verification methodologies for cutting-edge AI hardware.

You will write SystemVerilog/UVM test benches, develop test plans from architecture specs, and collaborate with architects, designers, and software engineers to deliver high-quality DV milestones and efficient testbenches.

Qualifications

• MS or higher in Computer or Electrical Engineering or equivalent experience.
• Experience in SystemVerilog, UVM, and OOPS-based programming.
• Strong coding skills in Python or other scripting languages.
• Understanding of RTL design (Verilog).
• Familiarity with verification tools like VCS and debug tools like Verdi.

Responsibilities

• Design and maintain the unit level/sub-system verification environment.
• Understand architecture specifications and develop test plans to verify designs.
• Create UVM components, sequences, tests, and scoreboards.
• Sign off on verification efforts ensuring high-quality code and functional coverage.
• Launch regressions, resolve issues, and progress towards DV milestone targets.
• Automate manual steps in launching builds, regressions, and triages.
• Collaborate with architects, designers, and software engineers to achieve project goals.
• Contribute to improving testbench efficiency by adopting the latest techniques.

Skills

Strong analytical skills

Excellent communication

Collaborative abilities

Education

MS in Computer or Electrical Engineering

Tools

VCS

Verdi

Job description

NVIDIA in Austin, TX is seeking an entry-level ASIC Verification Engineer to join our SOC group. You will help design and verify unit and sub-system blocks, build verification environments, and contribute to IP verification methodologies for cutting-edge AI hardware.

You will write SystemVerilog/UVM test benches, develop test plans from architecture specs, and collaborate with architects, designers, and software engineers to deliver high-quality DV milestones and efficient testbenches.