Principal Interconnect Design Engineer

SiFive; Boston (MA); On-site; USD 231,444 - 282,876; Full time

Benefits offered by this job

Healthcare and retirement plans

Paid time off

Variable compensation and equity

Job summary

SiFive is looking for a principal-level hardware engineer to enhance CPU and interconnect development. Applicants should have a background in RISC-V architecture and experience in RTL design. The role also involves working on scalable and customizable architectural solutions.

With a strong emphasis on collaboration, engineers will architect innovative designs that integrate efficiently within the existing framework. Competitive benefits and compensation are included.

Qualifications

• Knowledge of cache and cache coherency architectures is crucial.
• Experience with NoC or other interconnect fabrics preferred.
• Strong software engineering background is necessary.

Responsibilities

• Architect, design and implement TileLink interconnect and caches.
• Create self-configuring RTL generators in Chisel.
• Integrate designs into SiFive’s framework for documentation.

Skills

Cache architectures

Software engineering

Hardware design (Verilog/System Verilog/VHDL)

Objective-oriented programming

Education

BS/MS in EE, CE, CS or related discipline

Tools

Git/Github

Jira

Confluence

Job description

SiFive is a leading RISC‑V technology company that develops high‑performance compute platforms for a wide range of applications.

Job Description

The Role: SiFive is looking for a principal‑level hardware engineer who is passionate about designing industry‑leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time‑to‑market by designing hardware as highly‑configurable generators. We leverage technology and ideas from the software industry to execute hardware design with the agility of software development.

We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance/evolve our existing IP as well as develop new IP.

Responsibilities

• Architect, design and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel
• Implement RTL generators such that elements self‑configure to optimally connect to each other
• Enhance future designs to provide higher performance, more efficient multi‑core and multi‑system coherence
• Design extensive configurability in as a first‑class consideration
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software
• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design

Qualifications

• Knowledge of cache and cache coherency architectures and concepts
• Experience with NoC or other interconnect fabrics
• Familiarity with industry‑standard bus protocols (AXI, AHB, APB, CHI, CXL, UCIe)
• Ability to architect solutions to connect bus fabrics of disparate protocols
• Strong software engineering skills/background, including:
  • Object‑oriented, aspect‑oriented, and particularly functional programming
  • Templated metaprogramming, in any language
  • Compiler infrastructures, particularly for domain‑specific languages
  • Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
  • Test‑driven development, particularly ability to write adaptive unit tests
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL
• Attention to detail and a focus on high‑quality design
• Ability to work well with others and a belief that engineering is a team sport
• BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience

Nice to Have

• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software
• Knowledge of RISC‑V architecture
• Experience with Git/Github, Jira, Confluence

Pay & Benefits

Base Pay Range: $231,444.00–$282,876.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

Equal Opportunity Employer

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.

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