Innovative Silicon Physical Design Engineer

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto, Northern (CA, KY); Hybrid; USD 135,000 - 210,000; Full time

Benefits offered by this job

Stock options

Bonuses

Comprehensive medical coverage

Vision and dental coverage

401(k) retirement plan

Generous paid time off

Job summary

SpaceX in Palo Alto, CA seeks a Physical Design Engineer to drive cutting‑edge ASIC implementation for space and ground systems. You will synthesize, floorplan and route blocks, work with cross‑disciplinary teams, and optimize timing, power and area for robust space‑flight chips.

The role emphasizes collaboration, scripting, and hands‑on design work across RTL to GDSII during critical program milestones, with strong compensation and benefits.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• Experience with RTL2GDSII physical design and/or physical design flow development.

Responsibilities

• Perform partition synthesis and physical implementation steps (synthesis, floorplanning, power/ground grid, place and route, timing, noise, signoff).
• Develop/improve physical design methodologies and automation scripts for implementation steps.
• Collaborate with the ASIC design team to drive timing, power and area targets and explore RTL/design tradeoffs.
• Resolve design/timing/congestion issues and drive execution.
• Run, debug, and fix signoff closure issues in STA, noise, physical verification, electromigration and voltage drop.

Skills

EDA tools

FinFET CMOS

Digital design basics

Power dissipation

Analog design basics

DFT/MBIST/LBIST

Scripting (Python, Bash, TCL)

Education

Bachelor's degree in EE, CE or CS

Tools

RTL2GDSII

Standard cell libraries

Job description

SpaceX in Palo Alto, CA seeks a Physical Design Engineer to drive cutting‑edge ASIC implementation for space and ground systems. You will synthesize, floorplan and route blocks, work with cross‑disciplinary teams, and optimize timing, power and area for robust space‑flight chips.

The role emphasizes collaboration, scripting, and hands‑on design work across RTL to GDSII during critical program milestones, with strong compensation and benefits.