Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Irvine (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

Three weeks of paid vacation

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP is seeking a Sr. SOC/ASIC Physical Design Engineer in Irvine, CA. This role involves pioneering silicon technologies for space applications, coordinating with cross-disciplinary teams, and pushing the limits of performance for the Starlink network.

The ideal candidate possesses a Bachelor's degree and over 5 years of ASIC/physical design experience. The compensation ranges from $160,000 to $220,000, alongside a comprehensive benefits package including medical and retirement options.

Qualifications

• 5+ years of ASIC and/or physical design flow development experience in industry.
• Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows.

Responsibilities

• Perform partition synthesis and physical implementation steps.
• Develop/improve physical design methodologies and automation scripts.
• Collaborate closely with the ASIC design team.
• Resolve design/timing/congestion and flow issues.
• Run, debug, and fix signoff closure issues.

Skills

ASIC/SOC RTL2GDSII physical design and signoff flows

EDA tools

CMOS solid-state physics

CMOS digital design principles

power dissipation in deep sub-micron processes

Education

Bachelor’s degree in electrical engineering, computer engineering or computer science

Tools

EDA tools

Job description

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Irvine, CA

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today, SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will develop cutting‑edge next‑generation silicon for deployment in space and ground infrastructures around the globe. These chips enable connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other sign‑off checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Collaborate closely with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE

• Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
• Strong experience with industry standard EDA tools, including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub‑micron FinFET and CMOS solid‑state physics
• Knowledge of CMOS digital design principles, basic standard cells, their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep sub‑micron processes (leakage/dynamic)
• Familiarity with CMOS analog circuit and physical design
• Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Self‑driven individual with a can‑do attitude, willingness to learn, and the ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS

• Ability to work extended hours and weekends as needed to meet critical project milestones
• To conform to U.S. Government export regulations, applicant must be a U.S. citizen, lawful permanent resident, refugee, asylee, or otherwise eligible to obtain required authorizations from the U.S. Department of State

COMPENSATION AND BENEFITS

Pay range: Physical Design Engineer/Senior: $160,000.00 – $220,000.00 per year.

Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. In addition, you will receive comprehensive medical, vision, and dental coverage, a 401(k) retirement plan, short‑ and long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue three weeks of paid vacation and will be eligible for ten or more paid holidays per year. Exempt employees are eligible for five days of sick leave per year.

EEO STATEMENT

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].