Physical Design Engineer - Silicon ASICs

Spacex; Austin (TX); Hybrid; USD 110,000 - 150,000; Full time

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) in Austin, TX to develop cutting-edge ASICs for space and ground infrastructure. The role collaborates with cross-disciplinary teams across systems, firmware, architecture, design, and validation to deliver next-generation chips.

You will drive partition synthesis, place-and-route, timing, and signoff tasks while advancing physical design methodologies and automation. Strong EDA knowledge and CMOS fundamentals are essential.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional RTL2GDSII physical design and/or physical design flow development.
• Experience with industry standard EDA tools.

Responsibilities

• Perform partition synthesis and physical implementation steps including synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks.
• Develop/improve physical design methodologies and automation scripts for various implementation steps.
• Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Skills

RTL2GDSII

Physical design flow

EDA tools

FinFET/CMOS physics

CMOS design principles

Power dissipation in submicron

DFT/MBIST/LBIST

Self-motivated team player

Education

Bachelor’s degree in electrical/computer engineering or computer science

Job description

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) in Austin, TX to develop cutting-edge ASICs for space and ground infrastructure. The role collaborates with cross-disciplinary teams across systems, firmware, architecture, design, and validation to deliver next-generation chips.

You will drive partition synthesis, place-and-route, timing, and signoff tasks while advancing physical design methodologies and automation. Strong EDA knowledge and CMOS fundamentals are essential.