Physical Design Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Long-term incentives

Stock or long-term cash awards

Discretionary bonuses

Employee Stock Purchase Plan

Medical, vision, dental

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) for Irvine, CA. You will work on cutting-edge ASICs for Starlink, collaborating with cross-disciplinary teams to deliver robust physical design solutions.

The role emphasizes partition synthesis, floorplanning, timing, power, area targets, and signoff. Strong scripting and EDA tool familiarity are required, with optional advanced design skills and weekend availability.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
• Develop/improve physical design methodologies and automation scripts for various implementation steps.
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Skills

RTL2GDSII

Scripting (Python, TCL, Bash)

Team collaboration

Education

Bachelor's degree in electrical engineering, computer engineering or computer science

Tools

EDA tools

Job description

Physical Design Engineer (Silicon Engineering)

Irvine, CA

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars.

PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub-micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:

• Level 1: $125,000.00 - $160,000.00
• Level 2: $145,000.00 - $195,000.00

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

• Long-term incentives, in the form of company stock or long-term cash awards
• Potential discretionary bonuses
• The ability to purchase additional stock at a discount through an Employee Stock Purchase Plan
• Access to comprehensive medical, vision, and dental coverage
• Access to a 401(k) retirement plan
• Short and long-term disability insurance
• Life insurance
• Paid parental leave
• Various other discounts and perks
• Accrual of 3 weeks of paid vacation
• Eligible for 10 or more paid holidays per year
• Paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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