Innovative DFT Engineer for Scalable ASIC/FPGA Testing

Begell House Inc.; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Life Insurance

401k

Job summary

Arrow Electronics is seeking a Design For Test Engineer IV to develop and optimize DFT strategies for complex electronic systems. You will architect and implement scan, BIST, and boundary-scan structures, create test plans, and drive test coverage across product lifecycles.

Collaboration with design, manufacturing, and quality teams will be essential to improve yield, reliability, and manufacturability at global scale.

Qualifications

• DFT or VLSI design coursework or certification.
• ISTQB or similar test/validation credentials (preferred).
• Professional Engineer (PE) or equivalent (preferred).
• Develop test plans, patterns, and coverage metrics for complex products.

Responsibilities

• Define and implement DFT strategies for complex electronic products and systems.
• Integrate scan, BIST, and boundary-scan structures into ASIC/FPGA and board-level designs.
• Develop test plans, patterns, and coverage metrics to ensure product quality and manufacturability.
• Collaborate with design, manufacturing, and quality teams to resolve test and yield issues.
• Analyze production and characterization data to improve test efficiency and product reliability.
• Automate test flows, pattern generation, and data analysis with scripting tools.
• Participate in design reviews, providing DFT requirements and feedback to cross-functional teams.
• Document DFT methods, test procedures, and best practices for global engineering teams.

Skills

DFT architecture

ATPG

Boundary-scan

BIST design

Scripting

Data analysis

Education

ISTQB credentials (preferred)

PE or equivalent (preferred)

DFT/VLSI coursework (preferred)

Tools

Synopsys/Cadence/Mentor

JTAG IEEE 1149.x

Python/TCL/Perl scripting

Job description

Arrow Electronics is seeking a Design For Test Engineer IV to develop and optimize DFT strategies for complex electronic systems. You will architect and implement scan, BIST, and boundary-scan structures, create test plans, and drive test coverage across product lifecycles.

Collaboration with design, manufacturing, and quality teams will be essential to improve yield, reliability, and manufacturability at global scale.