Senior DFT Engineer (IC) – Scan, ATPG & MBIST

Arrow Electronics; San Jose (CA); On-site; USD 95,900 - 170,500; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with Matching

Disability Insurance

HSA/HRA Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Job summary

Arrow Electronics’ eInfochips division in San Jose, CA is seeking a Design For Test Engineer III (IC) to advance DFT for 3nm and 5nm Networking chips. You will implement DFT, perform RTL checks, and drive scan-insertion and MBIST verification on multi‑million gate SoCs.

You will use Spyglass, Tessent, and advanced pattern simulations, plus scripting with Perl, Shell, and TCL to automate flows; collaboration with cross‑functional teams is essential and on-site work is required.

Qualifications

• 5–7 years of experience in DFT.
• Experience with Scan-Insertion, ATPG, GLS and pattern simulations.
• MBIST insertion and verification.
• IEEE 1149.1 JTAG insertion and verification.
• Scripting in Perl, Shell and TCL.
• Worked on multi‑million gate count SoCs in Networking/IPs.
• Experience with Mentor Tessent.

Responsibilities

• DFT implementation for 3nm and 5nm Networking chips and IP DFT work.
• RTL checks for scan-insertion compatibility using Spyglass.
• Scan-Insertion using Tessent TestKompress.
• ATPG pattern generation in compressed and uncompressed modes.
• Pattern simulation with and without timing for different corners.
• MBIST insertion and verification on top-level blocks.
• IEEE 1149.1 JTAG insertion and verification.
• Scripting with Perl, Shell, TCL; DAeRT flow automation.
• Makefile enhancement for flow automation.

Skills

DFT

ATPG

Scan-Insertion

GLS

Pattern Simulation

MBIST Insertion

JTAG Insertion

Perl

Shell

TCL

Mentor Tessent

Cadence Modus

Synopsys Tetramax

Education

B.Tech in Microelectronics/Electronics

M.Tech in Microelectronics/Electronics

Tools

Mentor Tessent

Cadence Modus

Synopsys Tetramax

Job description

Arrow Electronics’ eInfochips division in San Jose, CA is seeking a Design For Test Engineer III (IC) to advance DFT for 3nm and 5nm Networking chips. You will implement DFT, perform RTL checks, and drive scan-insertion and MBIST verification on multi‑million gate SoCs.

You will use Spyglass, Tessent, and advanced pattern simulations, plus scripting with Perl, Shell, and TCL to automate flows; collaboration with cross‑functional teams is essential and on-site work is required.