Impactful SoC DV Engineer – Wireless & Tape-out Ready

Apple Inc.; Sunnyvale (CA); On-site; USD 129,000 - 195,000; Full time

Job summary

Apple Inc. seeks a Design Verification Engineer to verify pre-silicon RTL for block and top-level SoC in a wireless silicon environment.

You will architect UVM-based testbenches, integrate complex VIPs, and drive coverage-driven verification with multi-team collaboration across DV, architecture, firmware, and IP delivery groups. Lead efforts on low-power/clock domains and high-speed interfaces like PCIe, AXI/NOC, and memory subsystems.

Qualifications

• Bachelor of Science in Electrical Engineering or equivalent.
• Experience in ASIC DV or pre-silicon RTL verification is preferred.
• Strong HDL/UVM knowledge and pre-silicon verification experience.

Responsibilities

• Verify pre-silicon RTL for block and top-level SoC.
• Architect and integrate UVM-based testbenches and VIPs.
• Develop coverage-driven verification plans from specs.
• Collaborate with DV methodology architects to improve flow.

Skills

Excellent communication

Problem solving

Team player

Education

Bachelor of Science in Electrical Engineering or equivalent degree

Tools

UVM

OVM

PCIe

Bus Fabric

NOC

AHB

AXI bus

Job description

Apple Inc. seeks a Design Verification Engineer to verify pre-silicon RTL for block and top-level SoC in a wireless silicon environment.

You will architect UVM-based testbenches, integrate complex VIPs, and drive coverage-driven verification with multi-team collaboration across DV, architecture, firmware, and IP delivery groups. Lead efforts on low-power/clock domains and high-speed interfaces like PCIe, AXI/NOC, and memory subsystems.