SoC Verification Engineer: Build Next-Gen Wireless DV

Apple; Sunnyvale (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Apple is seeking a Design Verification Engineer to verify complex SOCs and develop reusable UVM testbenches for wireless SoCs. The role involves pre-silicon RTL verification across block and top levels, collaborating with DV teams, architecture, SW and FW groups to deliver high-quality silicon.

You will work in a dynamic, multi-functional organization focused on advancing Wireless SoC technology. Responsibilities include crafting and productizing state-of-the-art DV methodologies, deploying new

Qualifications

• Bachelor’s degree in Electrical Engineering or an equivalent field.
• Dedicated hands-on ASIC DV experience across full ASIC cycle.
• Advanced HVL knowledge (UVM/OVM) with recent UVM experience.
• Experience taping out large SOC systems with embedded processors.
• Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI architectures in UVM.

Responsibilities

• Verify a set of complex SOCs with DV environments and reusable UVM testbenches.
• Collaborate with IP DV teams and other product groups to ensure tape-out readiness.
• Develop coverage-driven verification plans and achieve targeted coverage for SOCs.

Skills

ASIC DV experience

UVM

OVM

HVL methodology

Low power design

HW/FW verification

PCIe

NOC

AXI bus

UPF simulations

Education

Bachelor of Science in Electrical Engineering or equivalent degree

Tools

UPF simulations

Job description

Apple is seeking a Design Verification Engineer to verify complex SOCs and develop reusable UVM testbenches for wireless SoCs. The role involves pre-silicon RTL verification across block and top levels, collaborating with DV teams, architecture, SW and FW groups to deliver high-quality silicon.

You will work in a dynamic, multi-functional organization focused on advancing Wireless SoC technology. Responsibilities include crafting and productizing state-of-the-art DV methodologies, deploying new