R&D Engineer IC Design

Broadcom; San Jose (CA); On-site; USD 108,000 - 173,000; Full time

Benefits offered by this job

401(k) with company match

Employee stock purchase program (ESPP)

Paid time off

Job summary

Broadcom is seeking an experienced verification engineer to verify complex switch designs. You will develop SystemVerilog testbenches, create test plans, and run tests at both block and chip levels. The role includes creating ATE vectors and C-based diagnostic tests for silicon validation.

The ideal candidate has a Master’s degree in a relevant field and at least six years of DV experience, with strong scripting skills and knowledge of UVM. On-site work in San Jose, CA is expected.

Qualifications

• Master’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
• Minimum 6 years of work experience in Design Verification.
• Strong knowledge of verification methods, tools, and environments.
• Proficiency in SystemVerilog and scripting languages.
• Knowledge of UVM methodology is preferable.
• Knowledge of networking and switching concepts is a plus.

Responsibilities

• Create SystemVerilog-based testbenches, checkers, and transactors for RTL and gate-level designs.
• Develop and execute test plans for verification.
• Build and run ATE testing vectors and C-based diagnostic tests on silicon.
• Collaborate with design and validation teams to ensure coverage.

Skills

SystemVerilog

UVM

Scripting

Education

Master’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent

Tools

Testbenches

Job description

Job Description:

Engineer will be responsible for verification of complex switch designs. Responsibilities will include creating SystemVerilog-based verification environments (testbenches, checkers, transactors) as well as creating and executing testplans for verifications of RTL and gatesim-based designs at both the block and chip level. The engineer will also be tasked with creating ATE testing vectors, as well as C-based diagnostic tests to be run on the actual silicon.

Job Requirements:

• A Master’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
• A minimum of 6 years of work experience in Design Verification
• Strong knowledge and hands-on experience in verification methods, tools and environment
• Strong programming skills, including in System Verilog and scripts languages
• Knowledge and experience in UVM methodology is preferable
• Knowledge of networking and switching concept is a plus

Additional Job Description:

Compensation and Benefits:

The annual base salary range for this position is $108,000- $172,800

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.