IC Layout & Mask Design Engineer - Impact & Precision

Micron Technology, Inc.; Boise (ID); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Paid holidays

Job summary

Micron Technology, Inc. in Boise, Idaho, seeks a Layout/Mask Design Engineer to translate schematics into manufacturable layouts for memory products, ensuring compliance with process rules and performance targets.

You will create physical layouts of transistors, resistors, capacitors, and interconnects, and perform floorplanning for efficient die area use. The role involves routing, PDN design, LVS/DRC verification, and close collaboration with analog, digital, and process teams to optimize

Qualifications

• Requires knowledge of device physics and material characteristics affecting chip performance.
• Experience with electron microscopy (SEM) and thermodynamics related to leakage.
• Strong understanding of layout principles and design rules for manufacturability.

Responsibilities

• Design and implement physical layouts for digital, analog, and mixed-signal circuits in memory products.
• Translate schematics into manufacturable layouts that meet process rules, performance targets, and schedules.
• Create layouts of transistors, resistors, capacitors, and interconnects; perform block-level floorplanning and die area estimation.
• Perform routing, power bus design, and robust PDN development to ensure electrical performance and reliability.
• Verify LVS and DRC; ensure compliance with foundry process design rules; collaborate with cross-functional teams.
• Maintain layout documentation and participate in layout and design reviews; drive continuous improvement for manufacturability.

Skills

Device physics

Material characteristics

SEM analysis

Leakage thermodynamics

Education

Bachelor's degree in EE/CE/Materials Eng

Job description

Micron Technology, Inc. in Boise, Idaho, seeks a Layout/Mask Design Engineer to translate schematics into manufacturable layouts for memory products, ensuring compliance with process rules and performance targets.

You will create physical layouts of transistors, resistors, capacitors, and interconnects, and perform floorplanning for efficient die area use. The role involves routing, PDN design, LVS/DRC verification, and close collaboration with analog, digital, and process teams to optimize