Memory IC Layout & Mask Design Engineer

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and holidays

Income protection and family leave

Job summary

Micron Technology, Inc. is seeking a layout engineer to design physical layouts for digital, analog, and mixed-signal circuits used in memory products.

You will translate schematics into manufacturable layouts, perform block-level floor planning, optimize area and timing, and ensure layouts meet process rules while collaborating closely with cross-functional design teams. Responsibilities include routing, power bus design, PDN development, LVS/DRC verification, and maintaining layout

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Material Engineering, or related field.
• Device physics knowledge.
• Material characteristics affecting chip design performance.
• Electron microscopy (SEM) experience.
• Thermodynamics impacting leakage.

Responsibilities

• Design physical layouts for digital, analog, and mixed-signal circuits used in memory products.
• Translate schematics into manufacturable layouts that meet process rules and performance targets.
• Perform block-level floor planning and provide accurate die area estimates.
• Execute routing, power bus design, and PDN solutions for reliable layouts.
• Verify LVS/DRC and collaborate with cross-functional teams to optimize manufacturability.

Skills

Device physics

Chip design performance

Electron microscopy (SEM)

Thermodynamics

Education

Bachelor's in Electrical/Computer/Material Eng

Job description

Micron Technology, Inc. is seeking a layout engineer to design physical layouts for digital, analog, and mixed-signal circuits used in memory products.

You will translate schematics into manufacturable layouts, perform block-level floor planning, optimize area and timing, and ensure layouts meet process rules while collaborating closely with cross-functional design teams. Responsibilities include routing, power bus design, PDN development, LVS/DRC verification, and maintaining layout