Senior DRAM Design Engineer — Memory & IC Layout Lead

Micron Technology, Inc; Boise (ID); On-site; USD 100,000 - 130,000; Full time

Job summary

Micron Technology, Inc is seeking a Senior DRAM Design Engineer in Boise, Idaho. The role involves contributing to circuit design, layout, and verification while collaborating with various engineering groups to ensure product manufacturability.

Qualified candidates should have a BSEE or MSEE with at least four years of experience in Semiconductor Design. Expertise in modeling and simulation tools such as SPICE and Verilog is also essential.

Qualifications

• Minimum of 4 years relevant Semiconductor Design and Development experience.
• Experience in mixed design and product engineering.
• 3+ years in parasitic modeling and tape-out revisions.

Responsibilities

• Contribute to design, layout, verification of Memory/Logic/Analog circuits.
• Lead layout process including floor-planning and placement.
• Work with multiple engineering groups for manufacturability.

Skills

Modeling and simulation using SPICE

Verilog

Synopsys

Cadence Virtuoso

Education

BSEE or MSEE in Electrical Engineering

Job description

Micron Technology, Inc is seeking a Senior DRAM Design Engineer in Boise, Idaho. The role involves contributing to circuit design, layout, and verification while collaborating with various engineering groups to ensure product manufacturability.

Qualified candidates should have a BSEE or MSEE with at least four years of experience in Semiconductor Design. Expertise in modeling and simulation tools such as SPICE and Verilog is also essential.