DRAM Layout Engineer — Cadence Virtuoso Expert

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 90,000 - 130,000; Full time

Job summary

Micron Technology in Boise, Idaho is seeking a Layout Engineer to shape block-level layouts, guide physical design strategies, and influence DRAM product reliability.

You will build block-level layouts in Cadence Virtuoso, apply layout methods, verify against DRC/LVS, and support parasitic extraction and ECOs. A cross-site collaboration mindset is essential to drive quality across generations.

Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with cross-site teams.

Responsibilities

• Build block-level layouts in Cadence Virtuoso including floorplanning, placement, routing, and optimization
• Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy
• Ensure DRC, LVS, density, and reliability compliance
• Support parasitic extraction, post-layout verification, and ECO activities
• Create partial custom layouts for selected device-level or small analog blocks

Skills

Cadence Virtuoso

Physical layout

DRC/LVS knowledge

Cross-site collaboration

Job description

Micron Technology in Boise, Idaho is seeking a Layout Engineer to shape block-level layouts, guide physical design strategies, and influence DRAM product reliability.

You will build block-level layouts in Cadence Virtuoso, apply layout methods, verify against DRC/LVS, and support parasitic extraction and ECOs. A cross-site collaboration mindset is essential to drive quality across generations.