Memory Layout Engineer: Cadence Virtuoso Specialist

Micron Technology, Inc; Boise (ID); On-site; USD 80,000 - 100,000; Full time

Job summary

Micron Technology, Inc is seeking a dedicated Layout Engineer in Boise, Idaho to work on the physical design foundations behind their memory technologies. You will build block-level layouts, apply various layout methods, and ensure compliance with key design standards.

The ideal candidate has experience with Cadence Virtuoso, understands DRC and LVS, and is able to collaborate with global engineering teams. This role offers a chance to work on cutting-edge memory solutions.

Qualifications

• Experience performing physical layout in Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with teams.

Responsibilities

• Build block-level layouts in Cadence Virtuoso including placement and routing.
• Ensure DRC, LVS, density, and reliability compliance.
• Support parasitic extraction and post-layout verification.

Skills

Cadence Virtuoso

DRC and LVS compliance

Layout design and optimization

Job description

Micron Technology, Inc is seeking a dedicated Layout Engineer in Boise, Idaho to work on the physical design foundations behind their memory technologies. You will build block-level layouts, apply various layout methods, and ensure compliance with key design standards.

The ideal candidate has experience with Cadence Virtuoso, understands DRC and LVS, and is able to collaborate with global engineering teams. This role offers a chance to work on cutting-edge memory solutions.