Senior Design Verification Engineer

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 154,000 - 311,000; Full time

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive system-level verification ahead of silicon tape-out. You will build robust UVM testbenches, run constrained-random tests, and validate with emulation platforms such as Palladium/ZeBu/Veloce.

The role emphasizes collaboration with design and validation teams, coverage goals, and early software bring-up on hardware accelerators in a hybrid work model.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5–8 years of professional experience in design verification of digital/mixed-signal designs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Hands-on experience with emulation-based verification platforms (Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).
• Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.
• Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.
• Proficiency in debugging complex hardware designs using simulation and emulation tools.
• Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.
• Strong analytical and problem-solving skills with excellent attention to detail.

Responsibilities

• Develop and execute verification plans for IP-level and system-level designs.
• Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.
• Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.
• Set up, configure, and run designs on emulation platforms for system-level verification and performance validation.
• Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
• Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
• Develop and maintain assertion-based verification to complement simulation and emulation efforts.
• Drive coverage closure and generate verification sign-off reports.
• Support software and firmware teams with early bring-up activities on emulation platforms.
• Continuously improve verification processes, flows, and infrastructure.

Skills

SystemVerilog

UVM

Emulation platforms

Python

Perl

TCL

RTL design

Synthesis constraints

Timing analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree (preferred)

Tools

Cadence Palladium

Synopsys ZeBu

Mentor Veloce

Job description

## Senior Design Verification EngineerApplylocations: Sunnyvale, California, United States of Americatime type: Full timeposted on: Posted Yesterdayjob requisition id: 1208455Senior Design Verification EngineerThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.**Who We Are:**Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.**Job Description:**We are seeking a talented and driven **Senior** **Design Verification Engineer** with specialized knowledge and experience in **emulation-based verification** to join our engineering team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs, ensuring functional correctness and performance targets are met prior to silicon tape-out. You will work closely with design, architecture, and validation teams to define verification plans, build robust testbench environments, and drive coverage to closure. A key focus of this position is leveraging emulation-based platforms to accelerate system-level verification, enabling early software bring-up and full-chip validation at scale. This is an excellent opportunity for a verification professional looking to deepen their expertise in cutting-edge verification methodologies and emulation technologies.**Responsibilities*** Develop and execute verification plans for IP-level and system-level designs.* Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.* Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.* Set up, configure, and run designs on emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu, Mentor Veloce) for system-level verification and performance validation.* Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.* Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.* Develop and maintain assertion-based verification (SVA) to complement simulation and emulation efforts.* Drive coverage closure and generate verification sign-off reports.* Support software and firmware teams with early bring-up activities on emulation platforms.* Continuously improve verification processes, flows, and infrastructure.**Minimum Qualifications*** **Bachelor's degree** in Electrical Engineering, Computer Engineering, or Computer Science.* **5 – 8 years** of professional experience in design verification of digital/mixed-signal designs.* Strong proficiency in **SystemVerilog** and **UVM** methodology.* Hands-on experience with **emulation-based verification platforms** (e.g., Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).* Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.* Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.* Proficiency in debugging complex hardware designs using simulation and emulation tools.* Familiarity with scripting languages such as **Python**, **Perl**, or **TCL** for automation and flow development.* Strong analytical and problem-solving skills with excellent attention to detail.**Preferred Qualifications*** **Master's degree** in Electrical Engineering, Computer Engineering, or a related field.* Experience with **networking protocols** such as Ethernet (10G/25G/100G/400G), TCP/IP, PCIe, or CXL.* Knowledge of **communication and interface protocols** including AXI, AHB, APB, AMBA, I2C, SPI, or UART.* Experience with **formal verification** tools and techniques (e.g., JasperGold, VC Formal).* Familiarity with **FPGA prototyping** platforms and flows.* Experience with **power-aware verification** (UPF/CPF).* Prior exposure to **SoC-level verification** or full-chip integration verification.* Knowledge of **processor architectures** (ARM, RISC-V, x86) and software-driven verification techniques.* Experience with **continuous integration (CI)** and regression management frameworks.* Familiarity with **AI/ML application and architectures** and experience, such as, creating Gen AI skills, marketplace, agentic applications, etc.* Published work or patents in the area of design verification is a plus.**What We Can Offer You:****Health & Wellbeing**We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.**Personal & Professional Development**We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.**Unconditional Inclusion**We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.**Let's Stay Connected:**Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.#unitedstates### ### **Job:**Engineering**Job Level:**TCP\_04 "The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 153,500 - 310,500 in California The listed salary range reflects base salary. Variable incentives may also be offered."