Hybrid RTL Design & FPGA Integration Engineer

Socket.dev; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD is seeking an FPGA Product Development team member to drive RTL design and architecture for adaptive and embedded computing. You will apply Verilog/SystemVerilog, VLSI flow knowledge, and EDA tools to deliver optimized silicon and SW solutions.

You will collaborate across time zones with architects, hardware and software engineers, using AI-driven automation to accelerate IP integration and deliver robust verification and timely Silicon validation.

Qualifications

• RTL design in Verilog/SystemVerilog required.
• Understanding of VLSI design flow from RTL to physical design.
• Familiarity with physical implementation processes: floorplanning, synthesis, P&R, STA.
• Experience with EDA tools (Synopsys, Cadence, etc.).
• Knowledge of UVM verification and debugging.

Responsibilities

• Collaborate with architects, hardware engineers, and SW‑FW engineers to understand product requirements and features.
• Build early‑stage RTL designs based on product and architecture intent driving Silicon and Solution co‑development.
• Build and enhance AI‑driven infrastructure to accelerate IP integration and improve development timelines.
• Apply data‑driven methodologies to align engineering teams across next‑gen products and nodes.
• Support functional simulation and software quality checks, ensuring robust verification coverage.
• Partner with global teams to achieve seamless integration and delivery.

Skills

RTL design

VLSI design flow

EDA tools

UVM/OVM verification

FPGA architecture

Scripting

Education

Bachelor’s or Master’s in Computer Engineering or Electrical Engineering

Tools

Synopsys Design Compiler

Primetime

VCS

Cadence Virtuoso

Job description

AMD is seeking an FPGA Product Development team member to drive RTL design and architecture for adaptive and embedded computing. You will apply Verilog/SystemVerilog, VLSI flow knowledge, and EDA tools to deliver optimized silicon and SW solutions.

You will collaborate across time zones with architects, hardware and software engineers, using AI-driven automation to accelerate IP integration and deliver robust verification and timely Silicon validation.