Hybrid: Design Verification Engineer — AI Silicon & HPC

Acceler8 Talent; San Francisco (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Acceler8 Talent is seeking an experienced Design Verification Engineer to advance verification across blocks to system-level validation for high-performance silicon. You will own verification in subsystems and full-chip contexts, building robust testbenches and driving closures toward silicon milestones, in a hybrid SF Bay Area role.

Ideal candidates bring 5+ years in design verification, with knowledge of LPDDR/HBM and production experience with modern methodologies such as UVM, AVB, and formal

Qualifications

• Experience driving verification from concept-to-silicon.
• Knowledge of LPDDR/HBM.
• Production experience with verification methodologies (UVM, AVB, formal verification).
• Strong understanding of silicon micro-architecture and design concepts for high-performance compute, high-speed connectivity, memory management.

Responsibilities

• Contribute to verification methodology and execution across blocks, subsystems, full chip, and system-level validation.
• Own portions of verification execution at subsystem and chip level.
• Create testbenches and drive progress and verification closures toward silicon milestones.

Skills

UVM

AVB

Formal verification

Testbenches

LPDDR/HBM

Silicon debugging

Tools

Emulation platforms

Prototyping platforms

Job description

Acceler8 Talent is seeking an experienced Design Verification Engineer to advance verification across blocks to system-level validation for high-performance silicon. You will own verification in subsystems and full-chip contexts, building robust testbenches and driving closures toward silicon milestones, in a hybrid SF Bay Area role.

Ideal candidates bring 5+ years in design verification, with knowledge of LPDDR/HBM and production experience with modern methodologies such as UVM, AVB, and formal