Senior Design Verification Engineer - AI Accelerator

Acceler8 Talent; Mountain View (CA); Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

Acceler8 Talent is seeking a Design Verification Engineer in Mountain View, CA, to own verification from planning to functional closure for AI accelerator silicon. The role collaborates with RTL, software, and architecture teams and drives verification strategies across IP, subsystems, and full-chip environments.

The candidate should have 5+ years of pre-silicon verification experience, strong debugging skills, and a track record delivering milestones on aggressive schedules.

Qualifications

• 5+ years of pre-silicon design verification experience.
• Experience owning verification from planning to functional closure.
• Experience in block-level, subsystem, SoC, or IP verification.
• Strong debugging skills for complex IP, subsystem, or SoC designs.
• Deep experience with UVM and testbench architecture.
• Ability to collaborate across hardware, software, architecture, and verification teams.
• Willingness to adapt across multiple verification domains.
• Interest in improving verification methodologies using automation and AI-assisted tooling.

Responsabilités

• Own an entire verification and testing domain.
• Develop end-to-end verification strategies spanning IP, subsystem, SoC, and emulation environments.
• Drive verification planning, implementation, debug, and functional closure for complex accelerator silicon.
• Build and improve verification infrastructure, testbenches, and methodologies.
• Debug complex functional issues across IP, subsystem, and full-chip environments.
• Partner closely with RTL design, architecture, software, and other engineering teams.
• Use and develop AI-assisted tool flows to accelerate verification and emulation timelines.
• Adapt quickly across verification domains as designs and project requirements evolve.

Connaissances

End-to-end verification ownership

UVM methodology

Testbench architecture

IP/SoC verification

Debugging complex IP/SoC

Hardware-software collaboration

Automation/AI-assisted tooling

Verification planning

Emulation testing

NoC/DMA verification

Outils

Palladium

Veloce

Description du poste

Acceler8 Talent is seeking a Design Verification Engineer in Mountain View, CA, to own verification from planning to functional closure for AI accelerator silicon. The role collaborates with RTL, software, and architecture teams and drives verification strategies across IP, subsystems, and full-chip environments.

The candidate should have 5+ years of pre-silicon verification experience, strong debugging skills, and a track record delivering milestones on aggressive schedules.