Lead Formal Verification Engineer - AI Accelerator Silicon

Acceler8 Talent; Mountain View (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Acceler8 Talent is seeking a Formal Verification Engineer to lead the verification strategy for AI accelerator silicon in Mountain View, CA. You will own block- and SoC-level formal verification from architecture through bring-up, crafting SVA/PSL properties and robust verification environments.

You will debug complex proof failures with RTL teams, refine methodologies, and push AI-assisted verification workflows to drive faster convergence and higher confidence in silicon correctness.

Qualifications

• Master's degree (or equivalent) plus 8+ years of formal verification experience for complex SoCs.
• Deep expertise in formal verification methodologies, including property authoring (SVA/PSL), proof strategies, abstraction techniques, and convergence.
• Strong experience debugging formal failures and collaborating with RTL designers to resolve issues.
• Hands-on experience with industry-standard formal verification tools such as VC Formal, JasperGold, or equivalent.
• Strong understanding of modern digital design and microarchitecture.

Responsibilities

• Own block- and SoC-level formal verification for AI accelerator silicon, from property development through proof convergence.
• Develop SystemVerilog Assertions (SVA) and formal verification environments to verify complex microarchitectural and system-level behavior.
• Debug proof failures, identify root causes, and collaborate with RTL designers and architects to drive closure.
• Build and improve formal verification methodologies, infrastructure, and AI-assisted verification flows, including AI agents that accelerate proof generation and convergence.
• Apply formal techniques throughout the development cycle, from early architectural validation through silicon bring-up readiness.
• Partner closely with design, verification, and software teams to ensure robust, scalable hardware.

Skills

Formal verification

SVA/PSL

Proof strategies

Convergence

Debugging failures

Education

Master's degree or equivalent

Tools

Synopsys VC Formal

Cadence JasperGold

Job description

Acceler8 Talent is seeking a Formal Verification Engineer to lead the verification strategy for AI accelerator silicon in Mountain View, CA. You will own block- and SoC-level formal verification from architecture through bring-up, crafting SVA/PSL properties and robust verification environments.

You will debug complex proof failures with RTL teams, refine methodologies, and push AI-assisted verification workflows to drive faster convergence and higher confidence in silicon correctness.